/* SoC Configuration */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_ARCH_TIMER
-#define CONFIG_SYS_TEXT_BASE 0x0c001000
+#define CONFIG_SYS_TEXT_BASE 0x0c000000
#define CONFIG_SPL_TARGET "u-boot-spi.gph"
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000
#define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */
#define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE - \
GENERATED_GBL_DATA_SIZE)
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+#define SPL_MALLOC_F_SIZE CONFIG_SYS_MALLOC_F_LEN
+#else
+#define SPL_MALLOC_F_SIZE 0
+#endif
+
/* SPL SPI Loader Configuration */
#define CONFIG_SPL_PAD_TO 65536
#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8)
#define CONFIG_SPL_STACK_SIZE (8 * 1024)
#define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \
CONFIG_SYS_SPL_MALLOC_SIZE + \
+ SPL_MALLOC_F_SIZE + \
CONFIG_SPL_STACK_SIZE - 4)
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO
/* UART Configuration */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_MEM32
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
+#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
+#endif
#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE
#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE
-#define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6)
#define CONFIG_CONS_INDEX 1
+#ifndef CONFIG_SOC_K2G
+#define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6)
+#else
+#define CONFIG_SYS_NS16550_CLK clk_get_rate(uart_pll_clk) / 2
+#endif
+
/* SPI Configuration */
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6)
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define I2C_BUS_MAX 3
/* EEPROM definitions */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
/* EDMA3 */
#define CONFIG_TI_EDMA3
+#define DEFAULT_PMMC_BOOT_ENV \
+ "set_name_pmmc=setenv name_pmmc ti-sci-firmware-${soc_variant}.bin\0" \
+ "dev_pmmc=0\0" \
+ "get_pmmc_net=dhcp ${loadaddr} ${tftp_root}/${name_pmmc}\0" \
+ "get_pmmc_ramfs=run get_pmmc_net\0" \
+ "get_pmmc_mmc=load mmc ${bootpart} ${loadaddr} " \
+ "${bootdir}/${name_pmmc}\0" \
+ "get_pmmc_ubi=ubifsload ${loadaddr} ${bootdir}/${name_pmmc}\0" \
+ "run_pmmc=rproc init; rproc list; " \
+ "rproc load ${dev_pmmc} ${loadaddr} 0x${filesize}; " \
+ "rproc start ${dev_pmmc}\0" \
+
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
"get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
"get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \
"get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0" \
- "burn_uboot_spi=sf probe; sf erase 0 0x100000; " \
+ "burn_uboot_spi=sf probe; sf erase 0 0x80000; " \
"sf write ${loadaddr} 0 ${filesize}\0" \
"burn_uboot_nand=nand erase 0 0x100000; " \
"nand write ${loadaddr} 0 ${filesize}\0" \
"mtdparts=mtdparts=davinci_nand.0:" \
"1024k(bootloader)ro,512k(params)ro,-(ubifs)\0"
+#ifndef CONFIG_BOOTCOMMAND
#define CONFIG_BOOTCOMMAND \
"run init_${boot} get_fdt_${boot} get_mon_${boot} " \
"get_kern_${boot} run_mon run_kern"
+#endif
#define CONFIG_BOOTARGS \
-/* Linux interfacing */
-#define CONFIG_OF_BOARD_SETUP
-
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>
/* And no support for GPIO, yet.. */
#undef CONFIG_SPL_GPIO_SUPPORT
-#undef CONFIG_CMD_GPIO
/* we may include files below only after all above definitions */
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
+#ifndef CONFIG_SOC_K2G
#define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6)
+#else
+#define CONFIG_SYS_HZ_CLOCK external_clk[sys_clk]
+#endif
#endif /* __CONFIG_KS2_EVM_H */