* Platform/Board specific defs
*/
#define CONFIG_SYS_TIMERBASE 0x4802E000
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
/*
* NS16550 Configuration
/* SPL */
/* Defines for SPL */
-#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
- CONFIG_SPL_TEXT_BASE)
-/* Since SPL did pll and ddr initialization for us,
- * we don't need to do it twice.
- */
-
-/*
- * Disable MMC DM for SPL build and can be re-enabled after adding
- * DM support in SPL
- */
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_DM_MMC
-#undef CONFIG_TIMER
-#endif
#endif