malta: Rename CONFIG_MALTA to CONFIG_TARGET_MALTA

[platform/kernel/u-boot.git] / include / configs / ti816x_evm.h

diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index c2dfdeb..7b04292 100644 (file)
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h
@@ -13,30 +13,25 @@
 #include <asm/arch/omap.h>
 
 #define CONFIG_EXTRA_ENV_SETTINGS      \
-       DEFAULT_LINUX_BOOT_ENV \
-       "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
-       "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+       DEFAULT_LINUX_BOOT_ENV
 
 /* Clock Defines */
 #define V_OSCK          24000000    /* Clock output from T2 */
 #define V_SCLK          (V_OSCK >> 1)
 
 #define CONFIG_MAX_RAM_BANK_SIZE       (2048 << 20)    /* 2048MB */
-#define CONFIG_SYS_SDRAM_BASE          0x80000000
+#define CFG_SYS_SDRAM_BASE             0x80000000
 
 /**
  * Platform/Board specific defs
  */
-#define CONFIG_SYS_TIMERBASE    0x4802E000
-#define CONFIG_SYS_PTV          2   /* Divisor: 2^(PTV+1) => 8 */
+#define CFG_SYS_TIMERBASE    0x4802E000
 
 /*
  * NS16550 Configuration
  */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK      (48000000)
-#define CONFIG_SYS_NS16550_COM1     0x48024000  /* Base EVM has UART2 */
+#define CFG_SYS_NS16550_CLK      (48000000)
+#define CFG_SYS_NS16550_COM1     0x48024000  /* Base EVM has UART2 */
 
 /* allow overwriting serial config and ethaddr */
 
@@ -45,14 +40,13 @@
  * GPMC NAND block.  We support 1 device and the physical address to
  * access CS0 at is 0x8000000.
  */
-#define CONFIG_SYS_NAND_BASE           0x8000000
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CFG_SYS_NAND_BASE              0x8000000
 
 /* NAND: SPL related configs */
 
 /* NAND: device related configs */
 /* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ECCPOS         { 2, 3, 4, 5, 6, 7, 8, 9, \
+#define CFG_SYS_NAND_ECCPOS            { 2, 3, 4, 5, 6, 7, 8, 9, \
                                         10, 11, 12, 13, 14, 15, 16, 17, \
                                         18, 19, 20, 21, 22, 23, 24, 25, \
                                         26, 27, 28, 29, 30, 31, 32, 33, \
@@ -60,12 +54,10 @@
                                         42, 43, 44, 45, 46, 47, 48, 49, \
                                         50, 51, 52, 53, 54, 55, 56, 57, }
 
-#define CONFIG_SYS_NAND_ECCSIZE                512
-#define CONFIG_SYS_NAND_ECCBYTES       14
+#define CFG_SYS_NAND_ECCSIZE           512
+#define CFG_SYS_NAND_ECCBYTES  14
 
 /* SPL */
 /* Defines for SPL */
-#define CONFIG_SPL_MAX_SIZE            (SRAM_SCRATCH_SPACE_ADDR - \
-                                        CONFIG_SPL_TEXT_BASE)
 
 #endif