#define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
/* USB/EHCI configuration */
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
/* Environment in SPI NOR flash */
"fdt_high=0x10000000\0" \
"initrd_high=0x10000000\0"
-/* SATA support */
-#define CONFIG_LBA48
-
-/* FPGA programming support */
-#define CONFIG_FPGA_STRATIX_V
-
/*
* Bootcounter
*/
/* SPL */
/* Defines for SPL */
-#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
-
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_SYS_SDRAM_SIZE SZ_2G