Merge tag 'u-boot-at91-2023.04-a' of https://source.denx.de/u-boot/custodians/u-boot...

[platform/kernel/u-boot.git] / include / configs / theadorable.h

diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
index c6a2cfe..2ce9284 100644 (file)
--- a/include/configs/theadorable.h
+++ b/include/configs/theadorable.h
@@ -6,6 +6,8 @@
 #ifndef _CONFIG_THEADORABLE_H
 #define _CONFIG_THEADORABLE_H
 
+#include <linux/sizes.h>
+
 /*
  * High Level Configuration Options (easy to change)
  */
@@ -15,7 +17,6 @@
  * for DDR ECC byte filling in the SPL before loading the main
  * U-Boot into it.
  */
-#define CONFIG_SYS_TCLK                250000000       /* 250MHz */
 
 /*
  * The debugging version enables USB support via defconfig.
@@ -24,36 +25,20 @@
  */
 
 /* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_MVTWSI
-#define CONFIG_I2C_MVTWSI_BASE0                MVEBU_TWSI_BASE
-#define CONFIG_I2C_MVTWSI_BASE1                MVEBU_TWSI1_BASE
-#define CONFIG_SYS_I2C_SLAVE           0x0
-#define CONFIG_SYS_I2C_SPEED           100000
+#define CFG_I2C_MVTWSI_BASE0           MVEBU_TWSI_BASE
+#define CFG_I2C_MVTWSI_BASE1           MVEBU_TWSI1_BASE
 
 /* USB/EHCI configuration */
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
 
 /* Environment in SPI NOR flash */
 
 #define PHY_ANEG_TIMEOUT       8000    /* PHY needs a longer aneg time */
 
 /* Keep device tree and initrd in lower memory so the kernel can access them */
-#define CONFIG_EXTRA_ENV_SETTINGS      \
+#define CFG_EXTRA_ENV_SETTINGS \
        "fdt_high=0x10000000\0"         \
        "initrd_high=0x10000000\0"
 
-/* SATA support */
-#define CONFIG_SYS_SATA_MAX_DEVICE     1
-#define CONFIG_LBA48
-
-/* Enable LCD and reserve 512KB from top of memory*/
-#define CONFIG_SYS_MEM_TOP_HIDE                0x80000
-
-/* FPGA programming support */
-#define CONFIG_FPGA_STRATIX_V
-
 /*
  * Bootcounter
  */
@@ -81,19 +66,8 @@
 
 /* SPL */
 /* Defines for SPL */
-#define CONFIG_SPL_MAX_SIZE            ((128 << 10) - 0x4030)
-
-#define CONFIG_SPL_BSS_START_ADDR      (0x40000000 + (128 << 10))
-#define CONFIG_SPL_BSS_MAX_SIZE                (16 << 10)
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MALLOC_SIMPLE
-#endif
-
-#define CONFIG_SPL_STACK               (0x40000000 + ((192 - 16) << 10))
-#define CONFIG_SPL_BOOTROM_SAVE                (CONFIG_SPL_STACK + 4)
 
 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_DDR_FIXED_SIZE          (2 << 20)       /* 2GiB */
+#define CFG_SYS_SDRAM_SIZE             SZ_2G
 
 #endif /* _CONFIG_THEADORABLE_H */