+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _CONFIG_THEADORABLE_H
/*
* High Level Configuration Options (easy to change)
*/
-#define CONFIG_DISPLAY_BOARDINFO_LATE
/*
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
* for DDR ECC byte filling in the SPL before loading the main
* U-Boot into it.
*/
-#define CONFIG_SYS_TEXT_BASE 0x00800000
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/*
#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_PHY_MARVELL /* there is a marvell phy */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
-#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_PREBOOT
/* Keep device tree and initrd in lower memory so the kernel can access them */
/*
* Bootcounter
*/
-#define CONFIG_BOOTCOUNT_LIMIT
-#define CONFIG_BOOTCOUNT_RAM
/* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
#define BOOTCOUNT_ADDR 0x1000
/* SPL */
/* Defines for SPL */
-#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40004030
#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
/* SPL related SPI defines */
-#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS