Convert CONFIG_USE_BOOTCOMMAND et al to Kconfig

[platform/kernel/u-boot.git] / include / configs / tegra210-common.h

diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h
index e6c8152..3ba12be 100644 (file)
--- a/include/configs/tegra210-common.h
+++ b/include/configs/tegra210-common.h
@@ -1,8 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2013-2015
  * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
  */
 
 #ifndef _TEGRA210_COMMON_H_
@@ -10,28 +9,12 @@
 
 #include "tegra-common.h"
 
-/* Cortex-A57 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 /*
  * NS16550 Configuration
  */
 #define V_NS16550_CLK          408000000       /* 408MHz (pllp_out0) */
 
 /*
- * Miscellaneous configurable options
- */
-#define CONFIG_STACKBASE       0x82800000      /* 40MB */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_SYS_TEXT_BASE   0x8010E000
-
-/* Generic Interrupt Controller */
-#define CONFIG_GICV2
-
-/*
  * Memory layout for where various images get loaded by boot scripts:
  *
  * scriptaddr can be pretty much anywhere that doesn't conflict with something
@@ -55,23 +38,16 @@
  * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
  *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
  */
-#define CONFIG_LOADADDR 0x80080000
 #define MEM_LAYOUT_ENV_SETTINGS \
        "scriptaddr=0x90000000\0" \
        "pxefile_addr_r=0x90100000\0" \
-       "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
-       "fdt_addr_r=0x82000000\0" \
-       "ramdisk_addr_r=0x82100000\0"
-
-/* Defines for SPL */
-#define CONFIG_SPL_TEXT_BASE           0x80108000
-#define CONFIG_SYS_SPL_MALLOC_START    0x80090000
-#define CONFIG_SPL_STACK               0x800ffffc
+       "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+       "fdtfile=" FDTFILE "\0" \
+       "fdt_addr_r=0x83000000\0" \
+       "ramdisk_addr_r=0x83420000\0"
 
 /* For USB EHCI controller */
-#define CONFIG_EHCI_IS_TDI
 #define CONFIG_USB_EHCI_TXFIFO_THRESH  0x10
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
 
 /* GPU needs setup */
 #define CONFIG_TEGRA_GPU