ARM: Move SYS_CACHELINE_SIZE over to Kconfig

[platform/kernel/u-boot.git] / include / configs / tegra20-common.h

diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index 0841f33..793310f 100644 (file)
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -9,9 +9,6 @@
 #define _TEGRA20_COMMON_H_
 #include "tegra-common.h"
 
-/* Cortex-A9 uses a cache line size of 32 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE      32
-
 /*
  * Errata configuration
  */
@@ -32,7 +29,7 @@
 /*-----------------------------------------------------------------------
  * Physical Memory Map
  */
-#define CONFIG_SYS_TEXT_BASE   0x0010E000
+#define CONFIG_SYS_TEXT_BASE   0x00110000
 
 /*
  * Memory layout for where various images get loaded by boot scripts: