Merge remote-tracking branch 'u-boot/master'
[platform/kernel/u-boot.git] / include / configs / tegra20-common.h
index 769728b..098cdb4 100644 (file)
@@ -43,8 +43,6 @@
 
 #define CONFIG_SYS_CACHELINE_SIZE      32
 
-#define CONFIG_ARCH_CPU_INIT           /* Fire up the A9 core */
-
 #include <asm/arch/tegra20.h>          /* get chip and board defs */
 
 /*
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
 #define CONFIG_CMDLINE_TAG             /* enable passing of ATAGs */
 #define CONFIG_OF_LIBFDT               /* enable passing of devicetree */
 
-#ifdef CONFIG_TEGRA20_LP0
+#ifdef CONFIG_TEGRA_LP0
 #define TEGRA_LP0_ADDR                 0x1C406000
 #define TEGRA_LP0_SIZE                 0x2000
 #define TEGRA_LP0_VEC \
 /* Environment information, boards can override if required */
 #define CONFIG_CONSOLE_MUX
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define TEGRA20_DEVICE_SETTINGS        "stdin=serial\0" \
-                                       "stdout=serial\0" \
-                                       "stderr=serial\0"
+#define TEGRA_DEVICE_SETTINGS  "stdin=serial\0" \
+                               "stdout=serial\0" \
+                               "stderr=serial\0"
 
 #define CONFIG_LOADADDR                0x408000        /* def. location for kernel */
 #define CONFIG_BOOTDELAY       2               /* -1 to disable auto boot */
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE            (CONFIG_SYS_CBSIZE)
 
-#define CONFIG_SYS_MEMTEST_START       (TEGRA20_SDRC_CS0 + 0x600000)
+#define CONFIG_SYS_MEMTEST_START       (NV_PA_SDRC_CS0 + 0x600000)
 #define CONFIG_SYS_MEMTEST_END         (CONFIG_SYS_MEMTEST_START + 0x100000)
 
 #define CONFIG_SYS_LOAD_ADDR           (0xA00800)      /* default */
 #define CONFIG_SYS_HZ                  1000
 
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
 #define CONFIG_STACKBASE       0x2800000       /* 40MB */
-#define CONFIG_STACKSIZE       0x20000         /* 128K regular stack*/
 
 /*-----------------------------------------------------------------------
  * Physical Memory Map
  */
 #define CONFIG_NR_DRAM_BANKS   1
-#define PHYS_SDRAM_1           TEGRA20_SDRC_CS0
+#define PHYS_SDRAM_1           NV_PA_SDRC_CS0
 #define PHYS_SDRAM_1_SIZE      0x20000000      /* 512M */
 
-#define CONFIG_SYS_TEXT_BASE   0x00108000
+#define CONFIG_SYS_TEXT_BASE   0x0010c000
 #define CONFIG_SYS_SDRAM_BASE  PHYS_SDRAM_1
 
 #define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_STACKBASE
 #define CONFIG_CMD_GPIO
 #define CONFIG_CMD_ENTERRCM
 #define CONFIG_CMD_BOOTZ
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_TEXT_BASE           0x00108000
+#define CONFIG_SPL_MAX_SIZE            0x00004000
+#define CONFIG_SYS_SPL_MALLOC_START    0x00090000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x00010000
+#define CONFIG_SPL_STACK               0x000ffffc
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_LDSCRIPT            "$(CPUDIR)/tegra20/u-boot-spl.lds"
+
+#define CONFIG_SYS_NAND_SELF_INIT
+
 #endif /* __TEGRA20_COMMON_H */