/* Misc CPU related */
-/* general purpose I/O */
-#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
-#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
-
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID ATMEL_ID_SYS
* leaving the correct space for initial global data structure above
* that address while providing maximum stack area below.
*/
-#define CONFIG_SYS_INIT_SP_ADDR \
- (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
#endif
-/* Ethernet */
-#define CONFIG_RMII
-#define CONFIG_AT91_WANTS_COMMON_PHY
-
/* USB */
#if defined(CONFIG_BOARD_TAURUS)
#define CONFIG_USB_ATMEL
#endif /* #ifndef CONFIG_SPL_BUILD */
/* Defines for SPL */
-#define CONFIG_SPL_MAX_SIZE (31 * SZ_512)
-#define CONFIG_SPL_STACK (ATMEL_BASE_SRAM1 + SZ_16K)
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE
-#define CONFIG_SPL_BSS_MAX_SIZE (3 * SZ_512)
#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
-#define CONFIG_SYS_USE_NANDFLASH 1
-#define CONFIG_SPL_NAND_RAW_ONLY
-#define CONFIG_SPL_NAND_SOFTECC
#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
-#define CONFIG_SPL_ATMEL_SIZE
#define CONFIG_SYS_MASTER_CLOCK 132096000
#define AT91_PLL_LOCK_TIMEOUT 1000000
#define CONFIG_SYS_AT91_PLLA 0x202A3F01
#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
#define CONFIG_SYS_AT91_PLLB 0x10193F05
-#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
#endif