*/
/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
+#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
+#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
/* Misc CPU related */
* SDRAM: 1 bank, min 32, max 128 MB
* Initialized before u-boot gets started.
*/
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M)
+#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
+#define CFG_SYS_SDRAM_SIZE (128 * SZ_1M)
/*
* Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
* leaving the correct space for initial global data structure above
* that address while providing maximum stack area below.
*/
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
+#define CFG_SYS_INIT_RAM_SIZE 0x1000
+#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
/* NAND flash */
#ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
+#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CFG_SYS_NAND_MASK_ALE (1 << 21)
+#define CFG_SYS_NAND_MASK_CLE (1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC13
#endif
#if defined(CONFIG_BOARD_TAURUS)
-/* USB DFU support */
-
-#define CONFIG_USB_GADGET_AT91
-
/* DFU class support */
#define DFU_MANIFEST_POLL_TIMEOUT 25000
#endif
/* bootstrap in spi flash , u-boot + env + linux in nandflash */
#if defined(CONFIG_BOARD_AXM)
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \
"${gatewayip}:${netmask}:${hostname}:${netdev}::off\0" \
"addtest=setenv bootargs ${bootargs} loglevel=4 test\0" \
/* Defines for SPL */
-#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
-#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_SIZE SZ_512K
+#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
-#define CONFIG_SYS_NAND_SIZE (256 * SZ_1M)
-#define CONFIG_SYS_NAND_ECCSIZE 256
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCSIZE 256
+#define CFG_SYS_NAND_ECCBYTES 3
+#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
-#define CONFIG_SYS_MASTER_CLOCK 132096000
+#define CFG_SYS_MASTER_CLOCK 132096000
#define AT91_PLL_LOCK_TIMEOUT 1000000
-#define CONFIG_SYS_AT91_PLLA 0x202A3F01
-#define CONFIG_SYS_MCKR 0x1300
-#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
-#define CONFIG_SYS_AT91_PLLB 0x10193F05
+#define CFG_SYS_AT91_PLLA 0x202A3F01
+#define CFG_SYS_MCKR 0x1300
+#define CFG_SYS_MCKR_CSS (0x02 | CFG_SYS_MCKR)
+#define CFG_SYS_AT91_PLLB 0x10193F05
#endif