#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
-#define CONFIG_MISC_INIT_R
-
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (4 << 20)
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
/*
* Hardware drivers
/*
* TWL4030
*/
-#define CONFIG_TWL4030_LED
/*
* Board NAND Info.
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
- "if mmc rescan ${mmcdev}; then " \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
/* turn on command-line edit/hist/auto */
-#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */
/* defaults */
-#define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */
-#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
/* load address */
/*
* Physical Memory Map
*/
-#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10)
-#define CONFIG_ENV_OFFSET 0x260000
-#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
-#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
CONFIG_SPL_TEXT_BASE)