pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option

[platform/kernel/u-boot.git] / include / configs / t3corp.h

diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h
index 6115a5f..ff2189c 100644 (file)
--- a/include/configs/t3corp.h
+++ b/include/configs/t3corp.h
@@ -120,11 +120,16 @@
  */
 #define CONFIG_SYS_FLASH_CFI           /* The flash is CFI compatible  */
 #define CONFIG_FLASH_CFI_DRIVER                /* Use common CFI driver        */
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1       /* Use AMD reset cmd */
+#define CONFIG_SYS_FLASH_CFI_WIDTH     FLASH_CFI_16BIT
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method     */
+#define CONFIG_SYS_FLASH_PROTECTION    /* use hardware flash protection */
 
-#define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_BANKS     1       /* max num of memory banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE, \
+                       (CONFIG_SYS_FPGA1_BASE + 0x01000000) }
+#define CONFIG_SYS_CFI_FLASH_CONFIG_REGS { 0xffff,     /* don't set    */ \
+                       0xbddf }                /* set async read mode  */
+#define CONFIG_SYS_MAX_FLASH_BANKS     2       /* max num of memory banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      512     /* max num of sectors p. chip*/
 
 #define CONFIG_SYS_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase/ms*/
@@ -355,6 +360,7 @@
        "ramdisk_addr=fc200000\0"                                       \
        "pciconfighost=1\0"                                             \
        "pcie_mode=RP:RP\0"                                             \
+       "unlock=yes\0"                                                  \
        ""
 
 /*
@@ -370,6 +376,7 @@
  */
 /* General PCI */
 #define CONFIG_PCI                     /* include pci support          */
+#define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
 #define CONFIG_PCI_PNP                 /* do pci plug-and-play   */
 #define CONFIG_PCI_SCAN_SHOW           /* show pci devices on startup  */
 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
@@ -423,7 +430,7 @@
                                 EBC_BXAP_WBN_ENCODE(0)         |       \
                                 EBC_BXAP_WBF_ENCODE(0)         |       \
                                 EBC_BXAP_TH_ENCODE(1)          |       \
-                                EBC_BXAP_RE_DISABLED           |       \
+                                EBC_BXAP_RE_ENABLED            |       \
                                 EBC_BXAP_SOR_DELAYED           |       \
                                 EBC_BXAP_BEM_RW                |       \
                                 EBC_BXAP_PEN_DISABLED)
@@ -440,7 +447,7 @@
                                 EBC_BXAP_WBN_ENCODE(0)         |       \
                                 EBC_BXAP_WBF_ENCODE(0)         |       \
                                 EBC_BXAP_TH_ENCODE(1)          |       \
-                                EBC_BXAP_RE_DISABLED           |       \
+                                EBC_BXAP_RE_ENABLED            |       \
                                 EBC_BXAP_SOR_DELAYED           |       \
                                 EBC_BXAP_BEM_RW                |       \
                                 EBC_BXAP_PEN_DISABLED)
@@ -457,7 +464,7 @@
                                 EBC_BXAP_WBN_ENCODE(0)         |       \
                                 EBC_BXAP_WBF_ENCODE(0)         |       \
                                 EBC_BXAP_TH_ENCODE(1)          |       \
-                                EBC_BXAP_RE_DISABLED           |       \
+                                EBC_BXAP_RE_ENABLED            |       \
                                 EBC_BXAP_SOR_DELAYED           |       \
                                 EBC_BXAP_BEM_RW                |       \
                                 EBC_BXAP_PEN_DISABLED)