+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2012 Xilinx
* (C) Copyright 2017 Opal Kelly Inc.
*
* Configuration settings for the SYZYGY Hub development board
* See zynq-common.h for Zynq common configs
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_SYZYGY_HUB_H
#define __CONFIG_SYZYGY_HUB_H
-#define CONFIG_ZYNQ_I2C1
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x57
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
"fit_image=fit.itb\0" \
"bitstream_image=download.bit\0" \
"loadbit_addr=0x1000000\0" \
"jtagboot=echo TFTPing FIT to RAM... && " \
"tftpboot ${load_addr} ${fit_image} && " \
"bootm ${load_addr}\0" \
- DFU_ALT_INFO \
BOOTENV
#include <configs/zynq-common.h>