*/
#ifdef CONFIG_MACH_SUN9I
#define SDRAM_OFFSET(x) 0x2##x
-#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CFG_SYS_SDRAM_BASE 0x20000000
#elif defined(CONFIG_MACH_SUNIV)
#define SDRAM_OFFSET(x) 0x8##x
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
#else
#define SDRAM_OFFSET(x) 0x4##x
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CFG_SYS_SDRAM_BASE 0x40000000
/* V3s do not have enough memory to place code at 0x4a000000 */
#endif
* is known yet.
* H6 has SRAM A1 at 0x00020000.
*/
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS
+#define CFG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS
/* FIXME: this may be larger on some SoCs */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
+#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
-#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_0 CFG_SYS_SDRAM_BASE
#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
-/* mmc config */
-#define CONFIG_MMC_SUNXI_SLOT 0
-
/*
* Miscellaneous configurable options
*/
-/* standalone support */
-#define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR
-
/* FLASH and environment organization */
/*
#define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb"
#endif
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
CONSOLE_ENV_SETTINGS \
MEM_LAYOUT_ENV_SETTINGS \
MEM_LAYOUT_ENV_EXTRA_SETTINGS \