+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2012-2012 Henrik Nordstrom <henrik@henriknordstrom.net>
*
* Tom Cubie <tangliang@allwinnertech.com>
*
* Configuration settings for the Allwinner sunxi series of boards.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SUNXI_COMMON_CONFIG_H
#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */
-#ifdef CONFIG_SUNXI_HIGH_SRAM
/*
* The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is
* slightly bigger. Note that it is possible to map the first 32 KiB of the
* A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the
* undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and
* the 1 actually activates the mapping of the first 32 KiB to 0x00000000.
+ * A64 and H5 also has SRAM A1 at 0x00010000, but no magic remap register
+ * is known yet.
+ * H6 has SRAM A1 at 0x00020000.
*/
-#define CONFIG_SYS_INIT_RAM_ADDR 0x10000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x08000 /* FIXME: 40 KiB ? */
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR 0x0
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
-#endif
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS
+/* FIXME: this may be larger on some SoCs */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_NAND_MAX_ECCPOS 1664
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_MAX_NAND_DEVICE 8
-
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
#endif
#ifdef CONFIG_SPL_SPI_SUNXI
#define CONFIG_SPL_BOARD_LOAD_IMAGE
#endif
-#ifdef CONFIG_SUNXI_HIGH_SRAM
+/*
+ * We cannot use expressions here, because expressions won't be evaluated in
+ * autoconf.mk.
+ */
+#if CONFIG_SUNXI_SRAM_ADDRESS == 0x10000
#define CONFIG_SPL_TEXT_BASE 0x10060 /* sram start+header */
#define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */
#ifdef CONFIG_ARM64
#else
#define LOW_LEVEL_SRAM_STACK 0x00018000
#endif /* !CONFIG_ARM64 */
+#elif CONFIG_SUNXI_SRAM_ADDRESS == 0x20000
+#define CONFIG_SPL_TEXT_BASE 0x20060 /* sram start+header */
+#define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */
+/* end of SRAM A2 on H6 for now */
+#define LOW_LEVEL_SRAM_STACK 0x00118000
#else
#define CONFIG_SPL_TEXT_BASE 0x60 /* sram start+header */
#define CONFIG_SPL_MAX_SIZE 0x5fa0 /* 24KB on sun4i/sun7i */
/* Ethernet support */
#ifdef CONFIG_SUN4I_EMAC
-#define CONFIG_PHY_ADDR 1
#define CONFIG_MII /* MII PHY management */
#endif
#ifdef CONFIG_SUN7I_GMAC
-#define CONFIG_PHY_ADDR 1
#define CONFIG_MII /* MII PHY management */
#define CONFIG_PHY_REALTEK
#endif
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
#endif
-#ifdef CONFIG_USB_FUNCTION_MASS_STORAGE
-#endif
-
#ifdef CONFIG_USB_KEYBOARD
#define CONFIG_PREBOOT
#endif