Merge branch 'master' of /home/wd/git/u-boot/custodians

[platform/kernel/u-boot.git] / include / configs / stxxtc.h

diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h
index 0dbf4b7..7ba8b77 100644 (file)
--- a/include/configs/stxxtc.h
+++ b/include/configs/stxxtc.h
@@ -63,9 +63,9 @@
 
 #undef CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND                                                     \
-       "tftpboot; "                                                            \
-       "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
-       "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
+       "tftpboot; "                                                            \
+       "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
+       "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
        "bootm"
 
 #define CONFIG_AUTOSCRIPT
@@ -93,14 +93,15 @@
 
 #define        CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
 
-#define        CONFIG_NET_MULTI        1       /* the only way to get the FEC in */
+#define        CONFIG_NET_MULTI        1       /* the only way to get the FEC in */
 #define        FEC_ENET                1       /* eth.c needs it that way... */
 #undef CFG_DISCOVER_PHY
 #define CONFIG_MII             1
+#define CONFIG_MII_INIT                1
 #undef CONFIG_RMII
 
 #define CONFIG_ETHER_ON_FEC1   1
-#define CONFIG_FEC1_PHY                1       /* phy address of FEC */
+#define CONFIG_FEC1_PHY                1       /* phy address of FEC */
 #undef CONFIG_FEC1_PHY_NORXERR
 
 #define CONFIG_ETHER_ON_FEC2   1
@@ -200,20 +201,20 @@
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define        CFG_ENV_IS_IN_FLASH     1
-#define CFG_ENV_SECT_SIZE      0x10000
+#define        CONFIG_ENV_IS_IN_FLASH  1
+#define CONFIG_ENV_SECT_SIZE   0x10000
 
-#define        CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00000000)
-#define CFG_ENV_OFFSET         0
-#define        CFG_ENV_SIZE            0x4000
+#define        CONFIG_ENV_ADDR         (CFG_FLASH_BASE + 0x00000000)
+#define CONFIG_ENV_OFFSET              0
+#define        CONFIG_ENV_SIZE         0x4000
 
-#define CFG_ENV_ADDR_REDUND    (CFG_FLASH_BASE + 0x00010000)
-#define CFG_ENV_OFFSET_REDUND  0
-#define CFG_ENV_SIZE_REDUND    CFG_ENV_SIZE
+#define CONFIG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x00010000)
+#define CONFIG_ENV_OFFSET_REDUND       0
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
 
 #define CFG_FLASH_CFI          1
-#define CFG_FLASH_CFI_DRIVER   1
-#undef CFG_FLASH_USE_BUFFER_WRITE      /* use buffered writes (20x faster) */
+#define CONFIG_FLASH_CFI_DRIVER        1
+#undef CFG_FLASH_USE_BUFFER_WRITE      /* use buffered writes (20x faster) */
 #define CFG_MAX_FLASH_SECT     128     /* max number of sectors on one chip */
 #define CFG_MAX_FLASH_BANKS    2       /* max number of memory banks   */
 
@@ -282,11 +283,11 @@
 #if MPC8XX_HZ == 50000000
 #define CFG_PLPRCR     ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
                         (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
+                        PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 66666666
 #define CFG_PLPRCR     ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \
                         (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
+                        PLPRCR_TEXPS)
 #else
 #error unsupported CPU freq for XIN = 10MHz
 #endif
@@ -448,7 +449,7 @@
 /****************************************************************/
 
 /* NAND */
-#define CFG_NAND_LEGACY
+#define CONFIG_NAND_LEGACY
 #define CFG_NAND_BASE          NAND_BASE
 #define CONFIG_MTD_NAND_ECC_JFFS2
 #define CONFIG_MTD_NAND_VERIFY_WRITE
@@ -461,7 +462,7 @@
 #define ADDR_COLUMN            1
 #define ADDR_PAGE              2
 #define ADDR_COLUMN_PAGE       3
-#define NAND_ChipID_UNKNOWN    0x00
+#define NAND_ChipID_UNKNOWN    0x00
 #define NAND_MAX_FLOORS                1
 #define NAND_MAX_CHIPS         1
 
@@ -579,7 +580,6 @@ typedef unsigned int led_id_t;
 /* use board specific hardware */
 #undef CONFIG_WATCHDOG                 /* watchdog disabled            */
 #define CONFIG_HW_WATCHDOG
-#define CONFIG_SHOW_ACTIVITY
 
 /*****************************************************************************/
 
@@ -589,15 +589,10 @@ typedef unsigned int led_id_t;
 
 /*****************************************************************************/
 
-/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE    1
-
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE  8192
+/* pass open firmware flattened device tree */
+#define CONFIG_OF_LIBFDT       1
 
 #define OF_CPU                 "PowerPC,MPC870@0"
 #define OF_TBCLK               (MPC8XX_HZ / 16)
-#define CONFIG_OF_HAS_BD_T     1
-#define CONFIG_OF_HAS_UBOOT_ENV        1
 
 #endif /* __CONFIG_H */