+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2009
* Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SPEAR_COMMON_H
/* U-Boot Load Address */
/* Ethernet driver configuration */
-#define CONFIG_MII
#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
/* USBD driver configuration */
* CONFIG_PL01x_PORTS is defined in specific files
*/
#define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
-#define CONFIG_CONS_INDEX 0
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
57600, 115200 }
/* NAND FLASH Configuration */
#define CONFIG_SYS_NAND_SELF_INIT
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
#define CONFIG_NAND_FSMC
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_MISC_INIT_R
#define CONFIG_SYS_MEMTEST_START 0x00800000
#define CONFIG_SYS_MEMTEST_END 0x04000000
#define CONFIG_SYS_FLASH_EMPTY_INFO
/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x00000000
#define PHYS_SDRAM_1_MAXSIZE 0x40000000