#undef CONFIG_8xx_CONS_NONE
#define CONFIG_MII
-/* #define MII_DEBUG */
-/* #define CONFIG_FEC_ENET */
+#define CONFIG_MII_INIT 1
#undef CONFIG_ETHER_ON_FEC1
#define CONFIG_ETHER_ON_FEC2
#define FEC_ENET
-/* #define CONFIG_FEC2_PHY_NORXERR */
-/* #define CFG_DISCOVER_PHY */
-/* #define CONFIG_PHY_ADDR 0x1 */
#define CONFIG_FEC2_PHY 1
#define CONFIG_BAUDRATE 19200
/* use PLD CLK4 instead of brg */
-#undef CFG_SPC1920_SMC1_CLK4
+#define CFG_SPC1920_SMC1_CLK4
#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
#define CFG_8xx_CPUCLK_MIN 40000000
#define CFG_8xx_CPUCLK_MAX 133000000
-#define CFG_RESET_ADDRESS 0xf8000000
+#define CFG_RESET_ADDRESS 0xC0000000
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_LAST_STAGE_INIT
-
-#if 1
+#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
-#ifndef CONFIG_COMMANDS
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
- | CFG_CMD_ASKENV \
- | CFG_CMD_ECHO \
- | CFG_CMD_IMMAP \
- | CFG_CMD_JFFS2 \
- | CFG_CMD_PING \
- | CFG_CMD_DHCP \
- | CFG_CMD_IMMAP \
- | CFG_CMD_I2C \
- | CFG_CMD_MII)
- /* & ~( CFG_CMD_NET)) */
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-#endif /* !CONFIG_COMMANDS */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
/*
* Miscellaneous configurable options
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#ifdef CONFIG_CMD_DATE
+# define CONFIG_RTC_DS3231
+# define CFG_I2C_RTC_ADDR 0x68
+#endif
+
/*-----------------------------------------------------------------------
* I2C configuration
*/
-#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+#if defined(CONFIG_CMD_I2C)
/* enable I2C and select the hardware/software driver */
#undef CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
-#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CFG_SIUMCR (SIUMCR_FRC)
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
* FLASH timing:
*/
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
- OR_SCY_3_CLK | OR_EHTR | OR_BI)
+ OR_SCY_6_CLK | OR_EHTR | OR_BI)
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
* DSP Host Port Interface CS3
*/
#define CFG_SPC1920_HPI_BASE 0x90000000
-#define CFG_PRELIM_OR3_AM 0xF0000000
+#define CFG_PRELIM_OR3_AM 0xF8000000
-#define CFG_OR3_PRELIM (CFG_PRELIM_OR3_AM | \
+#define CFG_OR3 (CFG_PRELIM_OR3_AM | \
OR_G5LS | \
OR_SCY_0_CLK | \
OR_BI)
-#define CFG_BR3_PRELIM ((CFG_SPC1920_HPI_BASE & BR_BA_MSK) | \
+#define CFG_BR3 ((CFG_SPC1920_HPI_BASE & BR_BA_MSK) | \
BR_MS_UPMA | \
BR_PS_16 | \
BR_V);
#define HPI_REG(x) (*((volatile u16 *) (CFG_SPC1920_HPI_BASE + x)))
#define HPI_HPIC_1 HPI_REG(0)
#define HPI_HPIC_2 HPI_REG(2)
-#define HPI_HPIA_1 HPI_REG(0x2000000)
-#define HPI_HPIA_2 HPI_REG(0x2000000 + 2)
-#define HPI_HPID_INC_1 HPI_REG(0x1000000)
-#define HPI_HPID_INC_2 HPI_REG(0x1000000 + 2)
-#define HPI_HPID_NOINC_1 HPI_REG(0x3000000)
-#define HPI_HPID_NOINC_2 HPI_REG(0x3000000 + 2)
+#define HPI_HPIA_1 HPI_REG(0x2000008)
+#define HPI_HPIA_2 HPI_REG(0x2000008 + 2)
+#define HPI_HPID_INC_1 HPI_REG(0x1000004)
+#define HPI_HPID_INC_2 HPI_REG(0x1000004 + 2)
+#define HPI_HPID_NOINC_1 HPI_REG(0x300000c)
+#define HPI_HPID_NOINC_2 HPI_REG(0x300000c + 2)
#endif /* CONFIG_SPC1920_HPI_TEST */
/*
- * PLD CS5
+ * Ramtron FM18L08 FRAM 32KB on CS4
+ */
+#define CFG_SPC1920_FRAM_BASE 0x80100000
+#define CFG_PRELIM_OR4_AM 0xffff8000
+#define CFG_OR4 (CFG_PRELIM_OR4_AM | \
+ OR_ACS_DIV2 | \
+ OR_BI | \
+ OR_SCY_4_CLK | \
+ OR_TRLX)
+
+#define CFG_BR4 ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+
+/*
+ * PLD CS5
*/
#define CFG_SPC1920_PLD_BASE 0x80000000
-#define CFG_PRELIM_OR5_AM 0xfff00000
+#define CFG_PRELIM_OR5_AM 0xffff8000
#define CFG_OR5_PRELIM (CFG_PRELIM_OR5_AM | \
OR_CSNT_SAM | \
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-/* Machine type
-*/
-#define _MACH_8xx (_MACH_fads)
-
#endif /* __CONFIG_H */
projects / platform / kernel / u-boot.git / blobdiff