#ifndef __CONFIG_H
#define __CONFIG_H
-/* High Level Configuration Options */
-#define CONFIG_SOCRATES 1
-
/*
* Only possible on E500 Version 2 or newer cores.
*/
* in the README.mpc85xxads.
*/
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-
#define CFG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
#undef CFG_SYS_DRAM_TEST /* memory test, takes time */
#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
/* DDR Setup */
-
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
-#define CONFIG_VERY_BIG_RAM
/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */
#define CFG_SYS_PCI1_MEM_PHYS 0x80000000
#define CFG_SYS_PCI1_IO_PHYS 0xE2000000
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "TSEC1"
-#undef CONFIG_MPC85XX_FEC
-
-#define TSEC1_PHY_ADDR 0
-#define TSEC3_PHY_ADDR 1
-
-#define TSEC1_PHYIDX 0
-#define TSEC3_PHYIDX 0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC3_FLAGS TSEC_GIGABIT
-
-/* Options are: TSEC[0,1] */
-
/*
* Miscellaneous configurable options
*/
#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consdev=ttyS0\0" \
"uboot_file=/home/tftp/syscon3/u-boot.bin\0" \