Convert CONFIG_SF_DEFAULT_* to Kconfig

[platform/kernel/u-boot.git] / include / configs / socfpga_sr1500.h

diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h
index 64e1595..d9de075 100644 (file)
--- a/include/configs/socfpga_sr1500.h
+++ b/include/configs/socfpga_sr1500.h
@@ -1,17 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2015 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 #ifndef __CONFIG_SOCFPGA_SR1500_H__
 #define __CONFIG_SOCFPGA_SR1500_H__
 
 #include <asm/arch/base_addr_ac5.h>
 
-#define CONFIG_FAT_WRITE
-
-#define CONFIG_HW_WATCHDOG
-
 /* Memory configurations */
 #define PHYS_SDRAM_1_SIZE              0x40000000      /* 1GiB on SR1500 */
 
@@ -22,11 +17,9 @@
 /* Ethernet on SoC (EMAC) */
 #define CONFIG_PHY_INTERFACE_MODE      PHY_INTERFACE_MODE_RGMII
 /* The PHY is autodetected, so no MII PHY address is needed here */
-#define CONFIG_PHY_MARVELL
 #define PHY_ANEG_TIMEOUT       8000
 
 /* Environment */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
 
 /* Enable SPI NOR flash reset, needed for SPI booting */
 #define CONFIG_SPI_N25Q256A_RESET
@@ -34,9 +27,6 @@
 /*
  * Bootcounter
  */
-#define CONFIG_BOOTCOUNT_LIMIT
-/* last 2 lwords in OCRAM */
-#define CONFIG_SYS_BOOTCOUNT_ADDR      0xfffffff8
 #define CONFIG_SYS_BOOTCOUNT_BE
 
 /* Environment setting for SPI flash */
@@ -49,7 +39,6 @@
 #define CONFIG_ENV_SPI_CS      0
 #define CONFIG_ENV_SPI_MODE    SPI_MODE_3
 #define CONFIG_ENV_SPI_MAX_HZ  100000000       /* Use max of 100MHz */
-#define CONFIG_SF_DEFAULT_SPEED        100000000
 
 /*
  * The QSPI NOR flash layout on SR1500: