Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze

[platform/kernel/u-boot.git] / include / configs / socfpga_cyclone5.h

diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index b5a7a9a..27c2be9 100644 (file)
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -7,13 +7,17 @@
 #define __CONFIG_H
 
 #include <asm/arch/socfpga_base_addrs.h>
+#include "../../board/altera/socfpga/pinmux_config.h"
+#include "../../board/altera/socfpga/iocsr_config.h"
+#include "../../board/altera/socfpga/pll_config.h"
 
 /*
  * High level configuration
  */
+/* Virtual target or real hardware */
+#define CONFIG_SOCFPGA_VIRTUAL_TARGET
 
 #define CONFIG_ARMV7
-#define CONFIG_L2_OFF
 #define CONFIG_SYS_DCACHE_OFF
 #undef CONFIG_USE_IRQ
 
@@ -21,11 +25,12 @@
 #define CONFIG_SINGLE_BOOTLOADER
 #define CONFIG_SOCFPGA
 
+/* base address for .text section */
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_SYS_TEXT_BASE           0x08000040
-#define V_NS16550_CLK                  1000000
-#define CONFIG_BAUDRATE                        57600
-#define CONFIG_SYS_HZ                  1000
-#define CONFIG_TIMER_CLOCK_KHZ         2400
+#else
+#define CONFIG_SYS_TEXT_BASE           0x01000040
+#endif
 #define CONFIG_SYS_LOAD_ADDR           0x7fc0
 
 /* Console I/O Buffer Size */
@@ -154,7 +159,7 @@
 /* SDRAM Bank #1 */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000
 /* SDRAM memory size */
-#define PHYS_SDRAM_1_SIZE              0x80000000
+#define PHYS_SDRAM_1_SIZE              0x40000000
 
 #define PHYS_SDRAM_1                   CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_MEMTEST_START       0x00000000
@@ -170,8 +175,13 @@
 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
 #define CONFIG_CONS_INDEX               1
 #define CONFIG_SYS_NS16550_COM1                UART0_BASE
-
 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define V_NS16550_CLK                  1000000
+#else
+#define V_NS16550_CLK                  100000000
+#endif
+#define CONFIG_BAUDRATE                        115200
 
 /*
  * FLASH
@@ -184,18 +194,35 @@
 /* This timer use eosc1 where the clock frequency is fixed
  * throughout any condition */
 #define CONFIG_SYS_TIMERBASE           SOCFPGA_OSC1TIMER0_ADDRESS
-
 /* reload value when timer count to zero */
 #define TIMER_LOAD_VAL                 0xFFFFFFFF
+/* Timer info */
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_SYS_TIMER_RATE          2400000
+#else
+#define CONFIG_SYS_TIMER_RATE          25000000
+#endif
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER       (CONFIG_SYS_TIMERBASE + 0x4)
 
 #define CONFIG_ENV_IS_NOWHERE
 
 /*
+ * L4 Watchdog
+ */
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_HW_WATCHDOG_TIMEOUT_MS  2000
+#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_DW_WDT_BASE             SOCFPGA_L4WD0_ADDRESS
+/* Clocks source frequency to watchdog timer */
+#define CONFIG_DW_WDT_CLOCK_KHZ                25000
+
+
+/*
  * SPL "Second Program Loader" aka Initial Software
  */
 
 /* Enable building of SPL globally */
-#define CONFIG_SPL
 #define CONFIG_SPL_FRAMEWORK
 
 /* TEXT_BASE for linking the SPL binary */
@@ -222,4 +249,7 @@
 /* Support for lib/libgeneric.o in SPL binary */
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 
+/* Support for watchdog */
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+
 #endif /* __CONFIG_H */