Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master'

[platform/kernel/u-boot.git] / include / configs / socfpga_cyclone5.h

diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index d9eb5d9..262e744 100644 (file)
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -1,30 +1,23 @@
 /*
  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
 #include <asm/arch/socfpga_base_addrs.h>
+#include "../../board/altera/socfpga/pinmux_config.h"
+#include "../../board/altera/socfpga/iocsr_config.h"
+#include "../../board/altera/socfpga/pll_config.h"
 
 /*
  * High level configuration
  */
+/* Virtual target or real hardware */
+#define CONFIG_SOCFPGA_VIRTUAL_TARGET
 
 #define CONFIG_ARMV7
-#define CONFIG_L2_OFF
 #define CONFIG_SYS_DCACHE_OFF
 #undef CONFIG_USE_IRQ
 
@@ -32,11 +25,12 @@
 #define CONFIG_SINGLE_BOOTLOADER
 #define CONFIG_SOCFPGA
 
+/* base address for .text section */
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_SYS_TEXT_BASE           0x08000040
-#define V_NS16550_CLK                  1000000
-#define CONFIG_BAUDRATE                        57600
-#define CONFIG_SYS_HZ                  1000
-#define CONFIG_TIMER_CLOCK_KHZ         2400
+#else
+#define CONFIG_SYS_TEXT_BASE           0x01000040
+#endif
 #define CONFIG_SYS_LOAD_ADDR           0x7fc0
 
 /* Console I/O Buffer Size */
@@ -65,7 +59,7 @@
 #define CONFIG_SYS_BOOTMAPSZ           ((256*1024*1024) - (4*1024))
 
 #define CONFIG_SPL_RAM_DEVICE
-#define CONFIG_SPL_STACK (&__stack_start)
+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
 #define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
 #define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
 
@@ -129,7 +123,7 @@
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "verify=n\0" \
-       "loadaddr= " MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \
+       "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
        "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
                "bootm ${loadaddr} - ${fdt_addr}\0" \
        "bootimage=uImage\0" \
@@ -165,7 +159,7 @@
 /* SDRAM Bank #1 */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000
 /* SDRAM memory size */
-#define PHYS_SDRAM_1_SIZE              0x80000000
+#define PHYS_SDRAM_1_SIZE              0x40000000
 
 #define PHYS_SDRAM_1                   CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_MEMTEST_START       0x00000000
@@ -181,8 +175,13 @@
 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
 #define CONFIG_CONS_INDEX               1
 #define CONFIG_SYS_NS16550_COM1                UART0_BASE
-
 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define V_NS16550_CLK                  1000000
+#else
+#define V_NS16550_CLK                  100000000
+#endif
+#define CONFIG_BAUDRATE                        115200
 
 /*
  * FLASH
@@ -195,13 +194,31 @@
 /* This timer use eosc1 where the clock frequency is fixed
  * throughout any condition */
 #define CONFIG_SYS_TIMERBASE           SOCFPGA_OSC1TIMER0_ADDRESS
-
 /* reload value when timer count to zero */
 #define TIMER_LOAD_VAL                 0xFFFFFFFF
+/* Timer info */
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_SYS_TIMER_RATE          2400000
+#else
+#define CONFIG_SYS_TIMER_RATE          25000000
+#endif
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER       (CONFIG_SYS_TIMERBASE + 0x4)
 
 #define CONFIG_ENV_IS_NOWHERE
 
 /*
+ * L4 Watchdog
+ */
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_HW_WATCHDOG_TIMEOUT_MS  2000
+#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_DW_WDT_BASE             SOCFPGA_L4WD0_ADDRESS
+/* Clocks source frequency to watchdog timer */
+#define CONFIG_DW_WDT_CLOCK_KHZ                25000
+
+
+/*
  * SPL "Second Program Loader" aka Initial Software
  */
 
@@ -233,4 +250,7 @@
 /* Support for lib/libgeneric.o in SPL binary */
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 
+/* Support for watchdog */
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+
 #endif /* __CONFIG_H */