*/
#define PHYS_SDRAM_1 0x0
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
-#define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000
+#define CFG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
+#define CFG_SYS_INIT_RAM_ADDR 0xFFE00000
/* SPL memory allocation configuration, this is for FAT implementation */
-#define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
+#define CFG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
CONFIG_SYS_SPL_MALLOC_SIZE)
#endif
* at this address to not overwrite the bootcounter by checking, if the
* bootcounter address is located in the internal SRAM.
*/
-#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
- (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE)))
+#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CFG_SYS_INIT_RAM_ADDR) && \
+ (CONFIG_SYS_BOOTCOUNT_ADDR < (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE)))
#endif
/*
* in U-Boot pre-reloc is higher than in SPL.
*/
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/*
* U-Boot general configurations
/*
* Cache
*/
-#define CONFIG_SYS_L2_PL310
-#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
-
-/*
- * Ethernet on SoC (EMAC)
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_DW_ALTDESCRIPTOR
-#endif
+#define CFG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
/*
* L4 OSC1 Timer 0
*/
#ifndef CONFIG_TIMER
-#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
-#define CONFIG_SYS_TIMER_COUNTS_DOWN
-#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
-#ifndef CONFIG_SYS_TIMER_RATE
-#define CONFIG_SYS_TIMER_RATE 25000000
+#define CFG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
+#define CFG_SYS_TIMER_COUNTER (CFG_SYS_TIMERBASE + 0x4)
+#ifndef CFG_SYS_TIMER_RATE
+#define CFG_SYS_TIMER_RATE 25000000
#endif
#endif
/*
* L4 Watchdog
*/
-#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
#define CONFIG_DW_WDT_CLOCK_KHZ 25000
/*
- * MMC Driver
- */
-#ifdef CONFIG_CMD_MMC
-/* FIXME */
-/* using smaller max blk cnt to avoid flooding the limited stack we have */
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
-#endif
-
-/*
* NAND Support
*/
#ifdef CONFIG_NAND_DENALI
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
-#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
+#define CFG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
+#define CFG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
#endif
/*