#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
-#define CONFIG_SYS_GENERIC_BOARD
/* Virtual target or real hardware */
#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
/*
* Cache
*/
-#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 30000000
-#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_BAR
/*
* The base address is configurable in QSys, each board must specify the
#define CONFIG_DWMMC
#define CONFIG_SOCFPGA_DWMMC
#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
-#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3
-#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0
/* FIXME */
/* using smaller max blk cnt to avoid flooding the limited stack we have */
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
/*
* QSPI support
*/
-#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
-#define CONFIG_CADENCE_QSPI
/* Enable multiple SPI NOR flash manufacturers */
-#define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */
-#define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SPI_FLASH_MTD
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nor0=ff705000.spi"
#endif
/* QSPI reference clock */
#ifndef __ASSEMBLY__
#define CONFIG_CQSPI_DECODER 0
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH_BAR
-#endif
-#ifdef CONFIG_OF_CONTROL /* DW SPI is controlled via DT */
-#define CONFIG_DESIGNWARE_SPI
+/*
+ * Designware SPI support
+ */
#define CONFIG_CMD_SPI
-#endif
/*
* Serial Driver
*/
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
-#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 4096
/*