mmc: move CONFIG_GENERIC_MMC to Kconfig

[platform/kernel/u-boot.git] / include / configs / socfpga_common.h

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index d37e595..8bbe3c5 100644 (file)
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -15,8 +15,6 @@
  * High level configuration
  */
 #define CONFIG_DISPLAY_BOARDINFO_LATE
-#define CONFIG_ARCH_MISC_INIT
-#define CONFIG_ARCH_EARLY_INIT_R
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_CLOCKS
 
@@ -142,12 +140,7 @@
  * MMC Driver
  */
 #ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
 #define CONFIG_BOUNCE_BUFFER
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DWMMC
-#define CONFIG_SOCFPGA_DWMMC
-#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH        1024
 /* FIXME */
 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 #define CONFIG_SYS_MMC_MAX_BLK_COUNT   256     /* FIXME -- SPL only? */
@@ -208,6 +201,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_CQSPI_REF_CLK           cm_get_qspi_controller_clk_hz()
 #endif
 #define CONFIG_CQSPI_DECODER           0
+#define CONFIG_BOUNCE_BUFFER
 
 /*
  * Designware SPI support
@@ -309,7 +303,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  * 0xFFFF_FF00 ...... End of SRAM
  */
 #define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_RAM_DEVICE
 #define CONFIG_SPL_TEXT_BASE           CONFIG_SYS_INIT_RAM_ADDR
 #define CONFIG_SPL_MAX_SIZE            (64 * 1024)
 
@@ -320,7 +313,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME                "u-boot-dtb.img"
 #else
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION     1
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR        0x200 /* offset 512 sect (256k) */
 #endif
 #endif