arm: socfpga: Enable all FPGA config support for Arria 10

[platform/kernel/u-boot.git] / include / configs / socfpga_common.h

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 107c6d5..2c23ae5 100644 (file)
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -15,8 +15,6 @@
 #define CONFIG_DISPLAY_BOARDINFO_LATE
 #define CONFIG_CLOCKS
 
-#define CONFIG_CRC32_VERIFY
-
 #define CONFIG_SYS_BOOTMAPSZ           (64 * 1024 * 1024)
 
 #define CONFIG_TIMESTAMP               /* Print image info with timestamp */
@@ -32,9 +30,13 @@
 #define CONFIG_SYS_MALLOC_LEN          (64 * 1024 * 1024)
 #define CONFIG_SYS_MEMTEST_START       PHYS_SDRAM_1
 #define CONFIG_SYS_MEMTEST_END         PHYS_SDRAM_1_SIZE
-
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define CONFIG_SYS_INIT_RAM_ADDR       0xFFFF0000
 #define CONFIG_SYS_INIT_RAM_SIZE       0x10000
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SYS_INIT_RAM_ADDR       0xFFE00000
+#define CONFIG_SYS_INIT_RAM_SIZE       0x40000 /* 256KB */
+#endif
 #define CONFIG_SYS_INIT_SP_OFFSET              \
        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR                        \
@@ -102,9 +104,6 @@
  * FPGA Driver
  */
 #ifdef CONFIG_CMD_FPGA
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
-#define CONFIG_FPGA_SOCFPGA
 #define CONFIG_FPGA_COUNT              1
 #endif
 
@@ -128,7 +127,7 @@
 #define CONFIG_DESIGNWARE_WATCHDOG
 #define CONFIG_DW_WDT_BASE             SOCFPGA_L4WD0_ADDRESS
 #define CONFIG_DW_WDT_CLOCK_KHZ                25000
-#define CONFIG_HW_WATCHDOG_TIMEOUT_MS  30000
+#define CONFIG_WATCHDOG_TIMEOUT_MSECS  30000
 #endif
 
 /*
@@ -185,7 +184,6 @@ unsigned int cm_get_l4_sp_clk_hz(void);
 /* Enable multiple SPI NOR flash manufacturers */
 #ifndef CONFIG_SPL_BUILD
 #define CONFIG_SPI_FLASH_MTD
-#define CONFIG_CMD_MTDPARTS
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITIONS
 #define MTDIDS_DEFAULT                 "nor0=ff705000.spi.0"
@@ -207,20 +205,20 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  */
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE    -4
-#define CONFIG_SYS_NS16550_COM1                SOCFPGA_UART0_ADDRESS
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_SYS_NS16550_CLK         1000000
-#else
+#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#define CONFIG_SYS_NS16550_COM1                SOCFPGA_UART0_ADDRESS
 #define CONFIG_SYS_NS16550_CLK         100000000
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SYS_NS16550_COM1        SOCFPGA_UART1_ADDRESS
+#define CONFIG_SYS_NS16550_CLK         50000000
 #endif
 #define CONFIG_CONS_INDEX              1
 
 /*
  * USB
  */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2
-#endif
 
 /*
  * USB Gadget (DFU, UMS)
@@ -278,13 +276,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
                                "-@1536k(UBI)\0"
 #endif
 
-/* UBI and UBIFS support */
-#if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND)
-#define CONFIG_CMD_UBIFS
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-#endif
-
 /*
  * SPL
  *
@@ -298,7 +289,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  */
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_TEXT_BASE           CONFIG_SYS_INIT_RAM_ADDR
-#define CONFIG_SPL_MAX_SIZE            (64 * 1024)
+#define CONFIG_SPL_MAX_SIZE            CONFIG_SYS_INIT_RAM_SIZE
 
 /* SPL SDMMC boot support */
 #ifdef CONFIG_SPL_MMC_SUPPORT