*/
#define PHYS_SDRAM_1 0x0
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
-#define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
-#define CONFIG_SPL_PAD_TO 0x10000
+#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000
+#define CFG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
-#define CONFIG_SPL_PAD_TO 0x40000
+#define CFG_SYS_INIT_RAM_ADDR 0xFFE00000
/* SPL memory allocation configuration, this is for FAT implementation */
-#ifndef CONFIG_SYS_SPL_MALLOC_SIZE
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000
-#endif
-#define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
+#define CFG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
CONFIG_SYS_SPL_MALLOC_SIZE)
-#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE)
#endif
/*
* at this address to not overwrite the bootcounter by checking, if the
* bootcounter address is located in the internal SRAM.
*/
-#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
- (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE)))
-#define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR
-#else
-#define CONFIG_SPL_STACK \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
+#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CFG_SYS_INIT_RAM_ADDR) && \
+ (CONFIG_SYS_BOOTCOUNT_ADDR < (CFG_SYS_INIT_RAM_ADDR + \
+ CFG_SYS_INIT_RAM_SIZE)))
#endif
/*
* phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
* in U-Boot pre-reloc is higher than in SPL.
*/
-#if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
-#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR
-#else
-#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
-#endif
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/*
* U-Boot general configurations
*/
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
/* Print buffer size */
-#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
- /* Boot argument buffer size */
/*
* Cache
*/
-#define CONFIG_SYS_L2_PL310
-#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
-
-/*
- * Ethernet on SoC (EMAC)
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_DW_ALTDESCRIPTOR
-#endif
-
-/*
- * FPGA Driver
- */
-#ifdef CONFIG_CMD_FPGA
-#define CONFIG_FPGA_COUNT 1
-#endif
+#define CFG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
/*
* L4 OSC1 Timer 0
*/
#ifndef CONFIG_TIMER
-#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
-#define CONFIG_SYS_TIMER_COUNTS_DOWN
-#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
-#ifndef CONFIG_SYS_TIMER_RATE
-#define CONFIG_SYS_TIMER_RATE 25000000
+#define CFG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
+#define CFG_SYS_TIMER_COUNTER (CFG_SYS_TIMERBASE + 0x4)
+#ifndef CFG_SYS_TIMER_RATE
+#define CFG_SYS_TIMER_RATE 25000000
#endif
#endif
/*
* L4 Watchdog
*/
-#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
-#define CONFIG_DW_WDT_CLOCK_KHZ 25000
-
-/*
- * MMC Driver
- */
-#ifdef CONFIG_CMD_MMC
-/* FIXME */
-/* using smaller max blk cnt to avoid flooding the limited stack we have */
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
-#endif
+#define CFG_DW_WDT_CLOCK_KHZ 25000
/*
* NAND Support
*/
#ifdef CONFIG_NAND_DENALI
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
-#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
-#endif
-
-/*
- * QSPI support
- */
-/* QSPI reference clock */
-#ifndef __ASSEMBLY__
-unsigned int cm_get_qspi_controller_clk_hz(void);
-#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
+#define CFG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
+#define CFG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
#endif
/*
*/
#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
#define DFU_DEFAULT_POLL_TIMEOUT 300
-
-/* USB IDs */
-#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
-#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
#endif
/*
* 0xFFEz_zzzz ...... Malloc area (grows up to top)
* 0xFFE3_FFFF ...... End of SRAM (top)
*/
-#ifndef CONFIG_SPL_TEXT_BASE
-#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
-#endif
-
-/* SPL SDMMC boot support */
-#ifdef CONFIG_SPL_MMC
-#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-#endif
-#endif
/* SPL QSPI boot support */
#include <config_distro_bootcmd.h>
-#ifndef CONFIG_EXTRA_ENV_SETTINGS
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#ifndef CFG_EXTRA_ENV_SETTINGS
+#define CFG_EXTRA_ENV_SETTINGS \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
"bootm_size=0xa000000\0" \
"kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \