Merge branch 'master' of /home/wd/git/u-boot/master

[platform/kernel/u-boot.git] / include / configs / smdk2400.h

diff --git a/include/configs/smdk2400.h b/include/configs/smdk2400.h
index 6388be4..fd51219 100644 (file)
--- a/include/configs/smdk2400.h
+++ b/include/configs/smdk2400.h
@@ -4,7 +4,7 @@
  * (C) Copyright 2002
  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  * Marius Groeger <mgroeger@sysgo.de>
- * Gary Jennejohn <gj@denx.de>
+ * Gary Jennejohn <garyj@denx.de>
  *
  * Configuation settings for the SAMSUNG board.
  *
@@ -34,9 +34,10 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_ARM920T         1       /* This is an ARM920T core      */
-#define CONFIG_S3C2400         1       /* in a SAMSUNG S3C2400 SoC     */
-#define CONFIG_SMDK2400                1       /* on an SAMSUNG SMDK2400 Board */
+#define CONFIG_ARM920T 1       /* This is an ARM920T core      */
+#define CONFIG_S3C24X0 1       /* in a SAMSUNG S3C24x0-type SoC        */
+#define CONFIG_S3C2400 1       /* specifically a SAMSUNG S3C2400 SoC   */
+#define CONFIG_SMDK2400        1       /* on an SAMSUNG SMDK2400 Board */
 
 /* input clock of PLL */
 #define CONFIG_SYS_CLK_FREQ    12000000 /* SMDK2400 has 12 MHz input clock */
@@ -56,13 +57,15 @@
 /*
  * Hardware drivers
  */
-#define CONFIG_DRIVER_CS8900   1       /* we have a CS8900 on-board */
-#define CS8900_BASE            0x07000300 /* agrees with WIN CE PA */
-#define CS8900_BUS16           1 /* the Linux driver does accesses as shorts */
+#define CONFIG_NET_MULTI
+#define CONFIG_CS8900          /* we have a CS8900 on-board */
+#define CONFIG_CS8900_BASE     0x07000300 /* agrees with WIN CE PA */
+#define CONFIG_CS8900_BUS16    /* the Linux driver does accesses as shorts */
 
 /*
  * select serial console configuration
  */
+#define CONFIG_S3C24X0_SERIAL
 #define CONFIG_SERIAL1          1      /* we use SERIAL 1 on SAMSUNG */
 
 #undef CONFIG_HWFLOW                   /* include RTS/CTS flow control support */
@@ -137,13 +140,9 @@
 #define CONFIG_SYS_MEMTEST_START       0x0c000000      /* memtest works on     */
 #define CONFIG_SYS_MEMTEST_END         0x0e000000      /* 32 MB in DRAM        */
 
-#undef  CONFIG_SYS_CLKS_IN_HZ          /* everything, incl board info, in Hz */
-
 #define        CONFIG_SYS_LOAD_ADDR            0x0cf00000      /* default load address */
 
-/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
-/* it to wrap 100 times (total 1562500) to get 1 sec. */
-#define        CONFIG_SYS_HZ                   1562500
+#define        CONFIG_SYS_HZ                   1000
 
 /* valid baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }