ppc4xx: Remove cache definition from 4xx board config files

[platform/kernel/u-boot.git] / include / configs / sequoia.h

diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 3f75a44..72f01d9 100644 (file)
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -43,6 +43,14 @@
 #define CONFIG_SYS_CLK_FREQ    ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
                                33333333 : 33000000)
 
+#if 0
+/*
+ * 44x dcache supported is working now on sequoia, but we don't enable
+ * it yet since it needs further testing
+ */
+#define CONFIG_4xx_DCACHE                      /* enable dcache        */
+#endif
+
 #define CONFIG_BOARD_EARLY_INIT_F 1            /* Call board_early_init_f */
 #define CONFIG_MISC_INIT_R     1               /* Call misc_init_r     */
 
@@ -343,6 +351,11 @@
 #define CONFIG_CMD_USB
 #endif
 
+#ifndef CONFIG_RAINIER
+#define CFG_POST_FPU_ON                CFG_POST_FPU
+#else
+#define CFG_POST_FPU_ON                0
+#endif
 
 /* POST support */
 #define CONFIG_POST            (CFG_POST_MEMORY   | \
@@ -350,7 +363,7 @@
                                 CFG_POST_UART     | \
                                 CFG_POST_I2C      | \
                                 CFG_POST_CACHE    | \
-                                CFG_POST_FPU      | \
+                                CFG_POST_FPU_ON   | \
                                 CFG_POST_ETHER    | \
                                 CFG_POST_SPR)
 
@@ -395,7 +408,8 @@
  *----------------------------------------------------------------------*/
 /* General PCI */
 #define CONFIG_PCI                     /* include pci support          */
-#undef CONFIG_PCI_PNP                  /* do (not) pci plug-and-play   */
+#define CONFIG_PCI_PNP                 /* do pci plug-and-play   */
+#define CFG_PCI_CACHE_LINE_SIZE        0 /* to avoid problems with PNP */
 #define CONFIG_PCI_SCAN_SHOW           /* show pci devices on startup  */
 #define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
 
@@ -444,6 +458,8 @@
 #define CFG_EBC_PB2AP          0x24814580
 #define CFG_EBC_PB2CR          (CFG_BCSR_BASE | 0x38000)
 
+#define CFG_BCSR5_PCI66EN      0x80
+
 /*-----------------------------------------------------------------------
  * NAND FLASH
  *----------------------------------------------------------------------*/
@@ -452,15 +468,6 @@
 #define CFG_NAND_BASE          (CFG_NAND_ADDR + CFG_NAND_CS)
 #define CFG_NAND_SELECT_DEVICE  1      /* nand driver supports mutipl. chips   */
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- *----------------------------------------------------------------------*/
-#define CFG_DCACHE_SIZE                (32<<10)  /* For AMCC 440 CPUs                  */
-#define CFG_CACHELINE_SIZE     32            /* ...                                */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT    5             /* log base 2 of the above value  */
-#endif
-
 /*
  * Internal Definitions
  *