Merge with /home/stefan/git/u-boot/bamboo-nand

[platform/kernel/u-boot.git] / include / configs / sequoia.h

diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 29f3b40..23243a4 100644 (file)
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -33,13 +33,14 @@
  *----------------------------------------------------------------------*/
 /* This config file is used for Sequoia (440EPx) and Rainier (440GRx)  */
 #ifndef CONFIG_RAINIER
-#define CONFIG_SEQUOIA         1               /* Board is Sequoia     */
 #define CONFIG_440EPX          1               /* Specific PPC440EPx   */
 #else
 #define CONFIG_440GRX          1               /* Specific PPC440GRx   */
 #endif
 #define CONFIG_4xx             1               /* ... PPC4xx family    */
-#define CONFIG_SYS_CLK_FREQ    33000000        /* external freq to pll */
+/* Detect Sequoia PLL input clock automatically via CPLD bit           */
+#define CONFIG_SYS_CLK_FREQ    ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
+                               33333333 : 33000000)
 
 #define CONFIG_BOARD_EARLY_INIT_F 1            /* Call board_early_init_f */
 #define CONFIG_MISC_INIT_R     1               /* Call misc_init_r     */
@@ -75,9 +76,7 @@
  * Initial RAM & stack pointer
  *----------------------------------------------------------------------*/
 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache    */
-#define CFG_INIT_RAM_OCM       1               /* OCM as init ram      */
 #define CFG_INIT_RAM_ADDR      CFG_OCM_BASE    /* OCM                  */
-
 #define CFG_INIT_RAM_END       (4 << 10)
 #define CFG_GBL_DATA_SIZE      256             /* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
@@ -169,12 +168,19 @@
 /*
  * Now the NAND chip has to be defined (no autodetection used!)
  */
-#define CFG_NAND_PAGE_SIZE     (512)           /* NAND chip page size          */
+#define CFG_NAND_PAGE_SIZE     512             /* NAND chip page size          */
 #define CFG_NAND_BLOCK_SIZE    (16 << 10)      /* NAND chip block size         */
-#define CFG_NAND_PAGE_COUNT    (32)            /* NAND chip page count         */
-#define CFG_NAND_BAD_BLOCK_POS (5)             /* Location of bad block marker */
+#define CFG_NAND_PAGE_COUNT    32              /* NAND chip page count         */
+#define CFG_NAND_BAD_BLOCK_POS 5               /* Location of bad block marker */
 #undef CFG_NAND_4_ADDR_CYCLE                   /* No fourth addr used (<=32MB) */
 
+#define CFG_NAND_ECCSIZE       256
+#define CFG_NAND_ECCBYTES      3
+#define CFG_NAND_ECCSTEPS      (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
+#define CFG_NAND_OOBSIZE       16
+#define CFG_NAND_ECCTOTAL      (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
+#define CFG_NAND_ECCPOS                {0, 1, 2, 3, 6, 7}
+
 #ifdef CFG_ENV_IS_IN_NAND
 /*
  * For NAND booting the environment is embedded in the U-Boot image. Please take
@@ -381,9 +387,6 @@
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
-#define CFG_FLASH              CFG_FLASH_BASE
-#define CFG_NAND               0xD0000000
-#define CFG_CPLD               0xC0000000
 
 /*
  * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
@@ -392,25 +395,25 @@
 #define CFG_NAND_CS            3               /* NAND chip connected to CSx   */
 /* Memory Bank 0 (NOR-FLASH) initialization                                    */
 #define CFG_EBC_PB0AP          0x03017200
-#define CFG_EBC_PB0CR          (CFG_FLASH | 0xda000)
+#define CFG_EBC_PB0CR          (CFG_FLASH_BASE | 0xda000)
 
 /* Memory Bank 3 (NAND-FLASH) initialization                                   */
 #define CFG_EBC_PB3AP          0x018003c0
-#define CFG_EBC_PB3CR          (CFG_NAND | 0x1c000)
+#define CFG_EBC_PB3CR          (CFG_NAND_ADDR | 0x1c000)
 #else
 #define CFG_NAND_CS            0               /* NAND chip connected to CSx   */
 /* Memory Bank 3 (NOR-FLASH) initialization                                    */
 #define CFG_EBC_PB3AP          0x03017200
-#define CFG_EBC_PB3CR          (CFG_FLASH | 0xda000)
+#define CFG_EBC_PB3CR          (CFG_FLASH_BASE | 0xda000)
 
 /* Memory Bank 0 (NAND-FLASH) initialization                                   */
 #define CFG_EBC_PB0AP          0x018003c0
-#define CFG_EBC_PB0CR          (CFG_NAND | 0x1c000)
+#define CFG_EBC_PB0CR          (CFG_NAND_ADDR | 0x1c000)
 #endif
 
 /* Memory Bank 2 (CPLD) initialization                                         */
 #define CFG_EBC_PB2AP          0x24814580
-#define CFG_EBC_PB2CR          (CFG_CPLD | 0x38000)
+#define CFG_EBC_PB2CR          (CFG_BCSR_BASE | 0x38000)
 
 /*-----------------------------------------------------------------------
  * NAND FLASH