#include <asm/sizes.h>
/* LP0 suspend / resume */
-#define CONFIG_TEGRA2_LP0
+#define CONFIG_TEGRA_LP0
#define CONFIG_AES
#define CONFIG_TEGRA_PMU
#define CONFIG_TPS6586X_POWER
#define CONFIG_TEGRA_CLOCK_SCALING
-#include "tegra2-common.h"
+#include "tegra20-common.h"
/* Enable fdt support for Seaboard. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra2-seaboard
+#define CONFIG_DEFAULT_DEVICE_TREE tegra20-seaboard
#define CONFIG_OF_CONTROL
#define CONFIG_OF_SEPARATE
/* High-level configuration options */
-#define V_PROMPT "Tegra2 (SeaBoard) # "
-#define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Seaboard"
+#define V_PROMPT "Tegra20 (SeaBoard) # "
+#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Seaboard"
/* Board-specific serial config */
-#define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA2_ENABLE_UARTD
+#define CONFIG_TEGRA_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */
#define CONFIG_UART_DISABLE_GPIO GPIO_PI3
-/*
- * On Seaboard, SPIFLASH is muxed with UART4. The next 5 defines are
- * needed to work around that design error.
- */
-#define CONFIG_SPI_UART_SWITCH
-#define CONFIG_SPI_CORRUPTS_UART NV_PA_APB_UARTD_BASE
-#define CONFIG_SPI_CORRUPTS_UART_NR 3
-#define CONFIG_SPI_CORRUPTS_UART_DLY 2500
-#undef CONFIG_CMDLINE_EDITING /* avoid NUL in input buffer */
#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD
-#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
#define CONFIG_BOARD_EARLY_INIT_F
-/* SPI */
-#define CONFIG_TEGRA2_SPI
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_WINBOND
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-
/* I2C */
#define CONFIG_TEGRA_I2C
#define CONFIG_SYS_I2C_INIT_BOARD
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
-#define CONFIG_TEGRA2_MMC
+#define CONFIG_TEGRA_MMC
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
-/* Environment in SPI */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SPI_MAX_HZ 48000000
-#define CONFIG_ENV_SPI_MODE SPI_MODE_0
-
-#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-#define CONFIG_ENV_OFFSET (CONFIG_SPI_FLASH_SIZE - CONFIG_ENV_SECT_SIZE)
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET ((512 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 2
/* USB Host support */
#define CONFIG_USB_EHCI
/* USB networking support */
#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_USB_ETHER_ASIX
/* General networking support */
#define CONFIG_CMD_DHCP
/* Enable keyboard */
-#define CONFIG_TEGRA2_KEYBOARD
+#define CONFIG_TEGRA_KEYBOARD
#define CONFIG_KEYBOARD
-#undef TEGRA2_DEVICE_SETTINGS
-#define TEGRA2_DEVICE_SETTINGS "stdin=serial,tegra-kbc\0" \
- "stdout=serial\0" \
- "stderr=serial\0"
+#undef TEGRA_DEVICE_SETTINGS
+#define TEGRA_DEVICE_SETTINGS "stdin=serial,tegra-kbc\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0"
+
+#include "tegra-common-post.h"
+
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_TEGRA_NAND
-#include "tegra2-common-post.h"
+/* Max number of NAND devices */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+/* Somewhat oddly, the NAND base address must be a config option */
+#define CONFIG_SYS_NAND_BASE NV_PA_NAND_BASE
#endif /* __CONFIG_H */