Merge branch 'master' of git://git.denx.de/u-boot-at91

[platform/kernel/u-boot.git] / include / configs / sbc8641d.h

diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 09a9901..0012945 100644 (file)
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -49,6 +49,12 @@
 
 #define CONFIG_SYS_RESET_ADDRESS    0xfff00100
 
+/*
+ * virtual address to be used for temporary mappings.  There
+ * should be 128k free at this VA.
+ */
+#define CONFIG_SYS_SCRATCH_VA  0xe8000000
+
 #define CONFIG_PCI             1       /* Enable PCIE */
 #define CONFIG_PCI1            1       /* PCIE controler 1 (slot 1) */
 #define CONFIG_PCI2            1       /* PCIE controler 2 (slot 2) */
@@ -98,6 +104,9 @@
 #define CONFIG_SYS_CCSRBAR             0xf8000000      /* relocated CCSRBAR */
 #define CONFIG_SYS_IMMR                CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
 
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW    CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH   0x0
+
 #define CONFIG_SYS_PCI1_ADDR           (CONFIG_SYS_CCSRBAR+0x8000)
 #define CONFIG_SYS_PCI2_ADDR           (CONFIG_SYS_CCSRBAR+0x9000)
 
@@ -108,6 +117,7 @@
 #define CONFIG_SYS_DDR_SDRAM_BASE2     0x10000000      /* DDR bank 2 */
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_SYS_SDRAM_BASE2         CONFIG_SYS_DDR_SDRAM_BASE2
+#define CONFIG_SYS_MAX_DDR_BAT_SIZE    0x80000000      /* BAT mapping size */
 #define CONFIG_VERY_BIG_RAM
 
 #define MPC86xx_DDR_SDRAM_CLK_CNTL
@@ -224,6 +234,7 @@
 #define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
 #define CONFIG_SYS_MONITOR_BASE        TEXT_BASE       /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000     /* early monitor loc */
 
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
@@ -233,7 +244,6 @@
 
 #undef CONFIG_CLOCKS_IN_MHZ
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR       0x0fd00000      /* Initial RAM address */
@@ -425,6 +435,17 @@
 #define CONFIG_SYS_IBAT3L      (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT3U      CONFIG_SYS_DBAT3U
 
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+                                      | BATL_PP_RW | BATL_CACHEINHIBIT \
+                                      | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
+                                      | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+                                      | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
+#endif
+
 /*
  * BAT4         32M    Cache-inhibited, guarded
  * 0xe200_0000  16M    PCI-Express 1 I/O
@@ -456,6 +477,14 @@
 #define CONFIG_SYS_IBAT6L      ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT6U      CONFIG_SYS_DBAT6U
 
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY        (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+                                | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY        (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY        (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+                                | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY        CONFIG_SYS_DBAT6U_EARLY
+
 #define CONFIG_SYS_DBAT7L      0x00000000
 #define CONFIG_SYS_DBAT7U      0x00000000
 #define CONFIG_SYS_IBAT7L      0x00000000