doc: update reference to README.board

[platform/kernel/u-boot.git] / include / configs / sbc8548.h

diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index e52b3a9..ae2c003 100644 (file)
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -1,14 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2007,2009 Wind River Systems <www.windriver.com>
  * Copyright 2007 Embedded Specialties, Inc.
  * Copyright 2004, 2007 Freescale Semiconductor.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /*
  * sbc8548 board configuration file
- * Please refer to doc/README.sbc8548 for more info.
+ * Please refer to board/sbc8548/README for more info.
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
@@ -49,11 +48,7 @@
 #define CONFIG_FSL_PCI_INIT            /* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT    1      /* enable 64-bit PCI resources */
 #endif
-#ifdef CONFIG_PCIE1
-#define CONFIG_FSL_PCIE_RESET   1      /* need PCIe reset errata */
-#endif
 
-#define CONFIG_TSEC_ENET               /* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 
 #define CONFIG_INTERRUPTS              /* enable pci, srio, ddr interrupts */
@@ -85,7 +80,6 @@
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW    CONFIG_SYS_CCSRBAR
 
 /* DDR Setup */
-#undef CONFIG_FSL_DDR_INTERACTIVE
 #undef CONFIG_DDR_ECC                  /* only for ECC DDR module */
 /*
  * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
@@ -247,8 +241,6 @@
 
 #define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE    /* start of monitor */
 
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 
 /* CS5 = Local bus peripherals controlled by the EPLD */
@@ -386,7 +378,6 @@
 #define CONFIG_SYS_MALLOC_LEN          (1024 * 1024) /* Reserved for malloc */
 
 /* Serial Port */
-#define CONFIG_CONS_INDEX      1
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE    1
 #define CONFIG_SYS_NS16550_CLK         (400000000 / CONFIG_SYS_CLK_DIV)
@@ -452,7 +443,6 @@
 
 #if defined(CONFIG_TSEC_ENET)
 
-#define CONFIG_MII             1       /* MII PHY management */
 #define CONFIG_TSEC1   1
 #define CONFIG_TSEC1_NAME      "eTSEC0"
 #define CONFIG_TSEC2   1
@@ -472,20 +462,6 @@
 #define CONFIG_ETHPRIME                "eTSEC0"
 #endif /* CONFIG_TSEC_ENET */
 
-/*
- * Environment
- */
-#define CONFIG_ENV_SIZE                0x2000
-#if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */
-#define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE + 0x80000)
-#define CONFIG_ENV_SECT_SIZE   0x80000 /* 512K(one sector) for env */
-#elif CONFIG_SYS_TEXT_BASE == 0xfffa0000       /* Boot from 8MB soldered flash */
-#define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE + 0x40000)
-#define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K(one sector) for env */
-#else
-#warning undefined environment size/location.
-#endif
-
 #define CONFIG_LOADS_ECHO      1       /* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 
@@ -522,7 +498,7 @@
 
 #define CONFIG_IPADDR   192.168.0.55
 
-#define CONFIG_HOSTNAME         sbc8548
+#define CONFIG_HOSTNAME         "sbc8548"
 #define CONFIG_ROOTPATH         "/opt/eldk/ppc_85xx"
 #define CONFIG_BOOTFILE         "/uImage"
 #define CONFIG_UBOOTPATH /u-boot.bin   /* TFTP server */