Merge branch 'Makefile-next' of git://git.denx.de/u-boot-arm

[platform/kernel/u-boot.git] / include / configs / sbc8548.h

diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index c84b70a..9d436c6 100644 (file)
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -47,19 +47,11 @@
 
 #define CONFIG_TSEC_ENET               /* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
-#undef CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_DLL                 /* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING           /* Sets the 2T timing bit */
 
-#undef CONFIG_DDR_ECC                  /* only for ECC DDR module */
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER      /* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE          0xDeadBeef
 #define CONFIG_INTERRUPTS              /* enable pci, srio, ddr interrupts */
 
 #define CONFIG_FSL_LAW         1       /* Use common FSL init code */
 
-#define MPC85xx_DDR_SDRAM_CLK_CNTL     /* 85xx has clock control reg */
-
 #define CONFIG_SYS_CLK_FREQ    66000000 /* SBC8548 default SYSCLK */
 
 /*
@@ -94,13 +86,26 @@
 #define CFG_PCI2_ADDR  (CFG_CCSRBAR+0x9000)
 #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
 
-/*
- * DDR Setup
- */
-#define CFG_DDR_SDRAM_BASE     0x00000000      /* DDR is system memory*/
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#undef CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
+#undef CONFIG_DDR_SPD
+#undef CONFIG_DDR_ECC                  /* only for ECC DDR module */
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER      /* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE  0xDeadBeef
+
+#define CFG_DDR_SDRAM_BASE     0x00000000
 #define CFG_SDRAM_BASE         CFG_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS     1
+#define CONFIG_DIMM_SLOTS_PER_CTLR     1
+#define CONFIG_CHIP_SELECTS_PER_CTRL   2
 
-#define SPD_EEPROM_ADDRESS     0x51            /* DDR DIMM */
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS     0x51    /* CTLR 0 DIMM 0 */
 
 /*
  * Make sure required options are set
@@ -176,9 +181,9 @@
 #define CFG_FLASH_ERASE_TOUT   60000   /* Flash Erase Timeout (ms) */
 #define CFG_FLASH_WRITE_TOUT   500     /* Flash Write Timeout (ms) */
 
-#define CFG_MONITOR_BASE       TEXT_BASE       /* start of monitor */
+#define CFG_MONITOR_BASE       TEXT_BASE       /* start of monitor */
 
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
 #define CFG_FLASH_CFI
 #define CFG_FLASH_EMPTY_INFO
 
@@ -429,10 +434,10 @@
 /*
  * Environment
  */
-#define CFG_ENV_IS_IN_FLASH    1
-#define CFG_ENV_ADDR           (CFG_MONITOR_BASE + 0x40000)
-#define CFG_ENV_SECT_SIZE      0x40000 /* 256K(one sector) for env */
-#define CFG_ENV_SIZE           0x2000
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR                (CFG_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_SECT_SIZE   0x40000 /* 256K(one sector) for env */
+#define CONFIG_ENV_SIZE                0x2000
 
 #define CONFIG_LOADS_ECHO      1       /* echo on for serial download */
 #define CFG_LOADS_BAUD_CHANGE  1       /* allow baudrate change */