*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
-#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
/*
* Only possible on E500 Version 2 or newer cores.
#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_RFEN (1 << (31 - 1))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_RFCR16 (7 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_BL8 (1 << (31 - 23))
-#define CONFIG_SYS_LBC_LSDMR_WRC4 (0 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_CL3 (3 << (31 - 31))
-
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW (3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
-
-/*
* Common settings for all Local Bus SDRAM commands.
* At run time, either BSMA1516 (for CPU 1.1)
* or BSMA1617 (for CPU 1.0) (old)
* is OR'ed in too.
*/
-#define CONFIG_SYS_LBC_LSDMR_COMMON ( CONFIG_SYS_LBC_LSDMR_RFCR16 \
- | CONFIG_SYS_LBC_LSDMR_PRETOACT7 \
- | CONFIG_SYS_LBC_LSDMR_ACTTORW7 \
- | CONFIG_SYS_LBC_LSDMR_BL8 \
- | CONFIG_SYS_LBC_LSDMR_WRC4 \
- | CONFIG_SYS_LBC_LSDMR_CL3 \
- | CONFIG_SYS_LBC_LSDMR_RFEN \
+#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
+ | LSDMR_PRETOACT7 \
+ | LSDMR_ACTTORW7 \
+ | LSDMR_BL8 \
+ | LSDMR_WRC4 \
+ | LSDMR_CL3 \
+ | LSDMR_RFEN \
)
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_TSEC1_NAME "eTSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC1"
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC2"
-#define CONFIG_TSEC4
-#define CONFIG_TSEC4_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 1
-#define TSEC3_PHY_ADDR 2
-#define TSEC4_PHY_ADDR 3
+#define TSEC1_PHY_ADDR 0x19
+#define TSEC2_PHY_ADDR 0x1a
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-#define TSEC4_PHYIDX 0
+
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC2_FLAGS TSEC_GIGABIT
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
/* Options are: eTSEC[0-3] */
#define CONFIG_ETHPRIME "eTSEC0"
/*
* Miscellaneous configurable options
*/
+#define CONFIG_CMDLINE_EDITING /* undef to save memory */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_ETHADDR 02:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD
-#define CONFIG_HAS_ETH2
-#define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD
-#define CONFIG_HAS_ETH3
-#define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD
#endif
#define CONFIG_IPADDR 192.168.0.55