#define __CONFIG_H
/*
- * Top level Makefile configuration choices
- */
-#ifdef CONFIG_MK_PCI
-#define CONFIG_PCI
-#endif
-
-#ifdef CONFIG_MK_66
-#define PCI_66M
-#endif
-
-#ifdef CONFIG_MK_33
-#define PCI_33M
-#endif
-
-/*
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 Family */
#define CONFIG_MPC8349 1 /* MPC8349 specific */
#define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */
+#define CONFIG_SYS_TEXT_BASE 0xFF800000
+
/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
* physically empty. The board will automatically (i.e w/o jumpers)
* clock down to 33MHz if you insert a 33MHz PCI card.
*/
-#ifdef PCI_33M
+#ifdef CONFIG_PCI_33M
#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
#else /* 66M */
#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
#endif
#ifndef CONFIG_SYS_CLK_FREQ
-#ifdef PCI_33M
+#ifdef CONFIG_PCI_33M
#define CONFIG_SYS_CLK_FREQ 33000000
#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
#else /* 66M */
/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \
- (2 << BR_PS_SHIFT) | /* 32 bit port size */ \
+ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
BR_V) /* valid */
#define CONFIG_SYS_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_I2C1_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C2_OFFSET
-/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */
+/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
/* TSEC */
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#undef PCI_ONE_PCI1
#endif
-#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#define CONFIG_TSEC_ENET /* TSEC ethernet support */
#if defined(CONFIG_TSEC_ENET)
-#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
-#endif
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
#define CONFIG_SYS_SICRL SICRL_LDP_A
#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ENABLE_INSTRUCTION_CACHE)
/* #define CONFIG_SYS_HID0_FINAL (\
HID0_ENABLE_INSTRUCTION_CACHE |\
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
-#define CONFIG_ETHADDR 00:a0:1e:a0:13:8d
#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:a0:1e:a0:13:8e
#endif
-#define CONFIG_IPADDR 192.168.1.234
-
#define CONFIG_HOSTNAME SBC8349
-#define CONFIG_ROOTPATH /tftpboot/rootfs
-#define CONFIG_BOOTFILE uImage
-
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_ROOTPATH "/tftpboot/rootfs"
+#define CONFIG_BOOTFILE "uImage"
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */