mpc83xx: Get rid of CONFIG_SYS_DDR_BASE

[platform/kernel/u-boot.git] / include / configs / sbc8349.h

diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index b586282..709387e 100644 (file)
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -22,8 +22,6 @@
 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
 #undef CONFIG_MPC83XX_PCI2             /* support for 2nd PCI controller */
 
-#define CONFIG_SYS_IMMR                0xE0000000
-
 #undef CONFIG_SYS_DRAM_TEST            /* memory test, takes time */
 #define CONFIG_SYS_MEMTEST_START       0x00000000      /* memtest region */
 #define CONFIG_SYS_MEMTEST_END         0x00100000
@@ -48,9 +46,8 @@
  */
 #undef CONFIG_DDR_32BIT
 
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
                                DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 #define CONFIG_DDR_2T_TIMING
@@ -133,8 +130,6 @@
  * External Local Bus rate is
  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
-#define CONFIG_SYS_LCRR_DBYP   LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
 #define CONFIG_SYS_LBC_LBCR    0x00000000
 
 #undef CONFIG_SYS_LB_SDRAM     /* if board has SDRAM on local bus */