Convert CONFIG_SPL_STACK to Kconfig
[platform/kernel/u-boot.git] / include / configs / sama5d4ek.h
index 2ac47fd..d2466da 100644 (file)
@@ -1,10 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Configuration settings for the SAMA5D4EK board.
  *
  * Copyright (C) 2014 Atmel
  *                   Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __CONFIG_H
 #include "at91-sama5_common.h"
 
 /* SDRAM */
-#define CONFIG_NR_DRAM_BANKS           1
 #define CONFIG_SYS_SDRAM_BASE           0x20000000
 #define CONFIG_SYS_SDRAM_SIZE          0x20000000
 
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_INIT_SP_ADDR                0x218000
-#else
-#define CONFIG_SYS_INIT_SP_ADDR \
-       (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
-#endif
-
-#define CONFIG_SYS_LOAD_ADDR           0x22000000 /* load address */
-
-#ifdef CONFIG_CMD_SF
-#define CONFIG_SF_DEFAULT_SPEED                30000000
-#endif
-
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_NAND_ATMEL
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x80000000
 /* our ALE is AD21 */
 #define CONFIG_SYS_NAND_MASK_ALE       (1 << 21)
 /* our CLE is AD22 */
 #define CONFIG_SYS_NAND_MASK_CLE       (1 << 22)
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-/* PMECC & PMERRLOC */
-#define CONFIG_ATMEL_NAND_HWECC
-#define CONFIG_ATMEL_NAND_HW_PMECC
 #endif
 
 /* SPL */
-#define CONFIG_SPL_TEXT_BASE           0x200000
-#define CONFIG_SPL_MAX_SIZE            0x18000
 #define CONFIG_SPL_BSS_START_ADDR      0x20000000
-#define CONFIG_SPL_BSS_MAX_SIZE                0x80000
 #define CONFIG_SYS_SPL_MALLOC_START    0x20080000
 #define CONFIG_SYS_SPL_MALLOC_SIZE     0x80000
 
 #define CONFIG_SYS_MONITOR_LEN         (512 << 10)
 
-#ifdef CONFIG_SD_BOOT
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME                "u-boot.img"
-
-#elif CONFIG_SPI_BOOT
-#define CONFIG_SYS_SPI_U_BOOT_OFFS     0x10000
-
-#elif CONFIG_NAND_BOOT
-#define CONFIG_SPL_NAND_DRIVERS
-#define CONFIG_SPL_NAND_BASE
-#endif
-#define CONFIG_PMECC_CAP               8
-#define CONFIG_PMECC_SECTOR_SIZE       512
-#define CONFIG_SYS_NAND_U_BOOT_OFFS    0x40000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_SIZE      0x1000
-#define CONFIG_SYS_NAND_PAGE_COUNT     64
-#define CONFIG_SYS_NAND_OOBSIZE                224
-#define CONFIG_SYS_NAND_BLOCK_SIZE     0x40000
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS  0x0
-#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
-
 #endif