+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration settings for the SAMA5D3 Xplained board.
*
* Copyright (C) 2014 Atmel Corporation
* Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/hardware.h>
-
-#define CONFIG_SYS_TEXT_BASE 0x26f00000
-
-/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
-#define CONFIG_SYS_HZ 1000
-
-#define CONFIG_AT91FAMILY
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_DISPLAY_CPUINFO
-
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_OF_LIBFDT /* Device Tree support */
-
-/* general purpose I/O */
-#define CONFIG_AT91_GPIO
-
-/* serial console */
-#define CONFIG_ATMEL_USART
-#define CONFIG_USART_BASE ATMEL_BASE_DBGU
-#define CONFIG_USART_ID ATMEL_ID_DBGU
+#include <linux/sizes.h>
+#include "at91-sama5_common.h"
/*
* This needs to be defined for the OHCI code to work but it is defined as
* ATMEL_ID_UHPHS in the CPU specific header files.
*/
-#define ATMEL_ID_UHP ATMEL_ID_UHPHS
+#define ATMEL_ID_UHP 32
/*
* Specify the clock enable bit in the PMC_SCER register.
*/
-#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
-
-#define CONFIG_BOOTDELAY 3
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/* No NOR flash */
-#define CONFIG_SYS_NO_FLASH
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_LOADS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
+#define ATMEL_PMC_UHP (1 << 6)
/* SDRAM */
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x10000000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR 0x318000
+#else
#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
/* NAND flash */
-#define CONFIG_CMD_NAND
-
#ifdef CONFIG_CMD_NAND
-#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_BASE 0x60000000
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ONFI_DETECTION
-/* PMECC & PMERRLOC */
-#define CONFIG_ATMEL_NAND_HWECC
-#define CONFIG_ATMEL_NAND_HW_PMECC
-#define CONFIG_PMECC_CAP 4
-#define CONFIG_PMECC_SECTOR_SIZE 512
-#define CONFIG_CMD_NAND_TRIMFFS
-#define CONFIG_CMD_MTDPARTS
-
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#endif
-
-/* Ethernet Hardware */
-#define CONFIG_MACB
-#define CONFIG_RMII
-#define CONFIG_NET_MULTI
-#define CONFIG_NET_RETRY_COUNT 20
-#define CONFIG_MACB_SEARCH_PHY
-#define CONFIG_RGMII
-#define CONFIG_CMD_MII
-#define CONFIG_PHYLIB
-
-/* MMC */
-#define CONFIG_CMD_MMC
-
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_GENERIC_ATMEL_MCI
-#define CONFIG_ATMEL_MCI_8BIT
#endif
/* USB */
-#define CONFIG_CMD_USB
-
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00600000
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
-#define CONFIG_DOS_PARTITION
-#define CONFIG_USB_STORAGE
-#endif
-
-#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
-#define CONFIG_CMD_FAT
-#define CONFIG_FAT_WRITE
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
#endif
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-#if CONFIG_SYS_USE_NANDFLASH
-/* bootstrap + u-boot + env in nandflash */
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0xc0000
-#define CONFIG_ENV_OFFSET_REDUND 0x100000
-#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \
- "nand read 0x22000000 0x200000 0x600000;" \
- "bootz 0x22000000 - 0x21000000"
-#elif CONFIG_SYS_USE_MMC
-/* bootstrap + u-boot + env in sd card */
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET 0x2000
-#define CONFIG_ENV_SIZE 0x1000
-#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d3_xplained.dtb; " \
- "fatload mmc 0:1 0x22000000 zImage; " \
- "bootz 0x22000000 - 0x21000000"
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#else
-#define CONFIG_ENV_IS_NOWHERE
-#endif
-
-#ifdef CONFIG_SYS_USE_MMC
-#define CONFIG_BOOTARGS \
- "console=ttyS0,115200 earlyprintk " \
- "root=/dev/mmcblk0p2 rw rootwait"
-#else
-#define CONFIG_BOOTARGS \
- "console=ttyS0,115200 earlyprintk " \
- "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
- "256K(env),256k(evn_redundent),256k(spare)," \
- "512k(dtb),6M(kernel)ro,-(rootfs) " \
- "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
-#endif
+/* SPL */
+#define CONFIG_SPL_MAX_SIZE 0x18000
+#define CONFIG_SPL_BSS_START_ADDR 0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
-#define CONFIG_BAUDRATE 115200
+/* size of u-boot.bin to load */
+#define CONFIG_SYS_MONITOR_LEN (2 * SZ_512K)
-#define CONFIG_SYS_PROMPT "U-Boot> "
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+#elif CONFIG_NAND_BOOT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#endif
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
#endif