+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuation settings for the Renesas RSK2+SH7264 board
*
* Copyright (C) 2011 Renesas Electronics Europe Ltd.
* Copyright (C) 2008 Nobuhiro Iwamatsu
* Copyright (C) 2008 Renesas Solutions Corp.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __RSK7264_H
#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
-#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
/* Serial */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024)
/* Flash */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */
#define CONFIG_SYS_MAX_FLASH_BANKS 1
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 36000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)