#include "rockchip-common.h"
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#include <asm/arch-rockchip/hardware.h>
#include <linux/sizes.h>
#define CONFIG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xff000000
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_MALLOC_LEN (32 << 20)
-#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
-#define CONFIG_ROCKCHIP_STIMER_BASE 0xff830020
-#define COUNTER_FREQUENCY 24000000
#define CONFIG_IRAM_BASE 0xff8c0000
-#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
-#define CONFIG_SYS_LOAD_ADDR 0x00280000
-
-#define CONFIG_SPL_MAX_SIZE 0x60000
-#define CONFIG_SPL_BSS_START_ADDR 0x400000
-#define CONFIG_SPL_BSS_MAX_SIZE 0x20000
-#define CONFIG_SPL_STACK 0x00188000
-
-#ifndef CONFIG_SPL_BUILD
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x00500000\0" \
"pxefile_addr_r=0x00600000\0" \
BOOTENV
#endif
-
-#endif