#define PHY_ANEG_TIMEOUT 20000
/* MEMORY */
-#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
#define DRAM_RSV_SIZE 0x08000000
#define CONFIG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE)
#else
#define CONFIG_SPL_BSS_START_ADDR 0xe631f000
#endif
-#define CONFIG_SPL_STACK 0xe6304000
#endif /* __RCAR_GEN3_COMMON_H */