#define __CONFIG_QI_LB60_H
#define CONFIG_MIPS32 /* MIPS32 CPU core */
+#define CONFIG_SYS_LITTLE_ENDIAN
#define CONFIG_JZSOC /* Jz SoC */
#define CONFIG_JZ4740 /* Jz4740 SoC */
#define CONFIG_NAND_JZ4740
#define CONFIG_SYS_UART_BASE JZ4740_UART0_BASE /* Base of the UART channel */
#define CONFIG_BAUDRATE 57600
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SYS_NAND_ECC_POS (6 * NANONOTE_NAND_SIZE)
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 9
-#define CONFIG_SYS_NAND_ECCSTEPS \
- (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
-#define CONFIG_SYS_NAND_ECCTOTAL \
- (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
#define CONFIG_SYS_NAND_ECCPOS \
{12, 13, 14, 15, 16, 17, 18, 19,\
20, 21, 22, 23, 24, 25, 26, 27, \
#define CONFIG_SYS_NAND_OOBSIZE 128
#define CONFIG_SYS_NAND_BASE 0xB8000000
#define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE
-#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/
#define CONFIG_NAND_SPL_TEXT_BASE 0x80000000