/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */
-#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONFIG_SYS_MEMTEST_START 0x10000000
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
-
/* MMC Configuration */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 1
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_ATHEROS
/* Framebuffer */
#define CONFIG_VIDEO_BMP_RLE8