#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_REISER
#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
#define CONFIG_CMD_USB
-
#define CONFIG_SUPPORT_VFAT
/*
/*-----------------------------------------------------------------------
* PPC440 GPIO Configuration
*/
-#define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
+#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
{ \
/* GPIO Core 0 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
} \
}
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
/*
* Internal Definitions
*
/* Offset for alternate registers */
#define CFG_ATA_ALT_OFFSET (0x0000)
-/* These addresses need to be shifted one place to the left
- * ( bus per_addr 20 -30 is connectsd on CF bus A10-A0)
- * These values are shifted
- */
-#define CFG_ATA_PORT_ADDR(port) ((port) << 1)
-
#endif /* __CONFIG_H */