Merge branch 'master' of git://git.denx.de/u-boot-sunxi

[platform/kernel/u-boot.git] / include / configs / pcm052.h

diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index 6021420..e125a38 100644 (file)
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -1,9 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
  * Configuration settings for the phytec PCM-052 SoM.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __CONFIG_H
@@ -32,19 +31,15 @@
 #define CONFIG_JFFS2_NAND
 
 /* Dynamic MTD partition support */
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_MTD_DEVICE
 
 #endif
 
-#define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
 #define CONFIG_SYS_FSL_ESDHC_NUM       1
 
 /*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/
 
 #define CONFIG_FEC_MXC
-#define CONFIG_MII
 #define IMX_FEC_BASE                   ENET_BASE_ADDR
 #define CONFIG_FEC_XCV_TYPE            RMII
 #define CONFIG_FEC_MXC_PHYADDR          0
@@ -63,7 +58,6 @@
 #define CONFIG_SYS_I2C_MXC
 
 /* RTC (actually an RV-4162 but M41T62-compatible) */
-#define CONFIG_RTC_M41T62
 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 #define CONFIG_SYS_RTC_BUS_NUM 2
 
@@ -76,7 +70,6 @@
 #define CONFIG_LOADADDR                        0x82000000
 
 /* We boot from the gfxRAM area of the OCRAM. */
-#define CONFIG_SYS_TEXT_BASE           0x3f401000
 #define CONFIG_BOARD_SIZE_LIMIT                520192
 
 /* if no target-specific extra environment settings were defined by the
@@ -187,9 +180,6 @@
                "nand write ${ram_addr} root ${filesize}; fi\0"
 
 /* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP            /* undef to save memory */
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_CMDLINE_EDITING
 
 #define CONFIG_SYS_MEMTEST_START       0x80010000
 #define CONFIG_SYS_MEMTEST_END         0x87C00000
@@ -197,7 +187,6 @@
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
 
 /* Physical memory map */
-#define CONFIG_NR_DRAM_BANKS           1
 #define PHYS_SDRAM                     (0x80000000)
 #define PHYS_SDRAM_SIZE                        (CONFIG_PCM052_DDR_SIZE * 1024 * 1024)