global: Migrate CONFIG_STACKBASE to CFG

[platform/kernel/u-boot.git] / include / configs / p2771-0000.h

diff --git a/include/configs/p2771-0000.h b/include/configs/p2771-0000.h
index 5523029..84cdd57 100644 (file)
--- a/include/configs/p2771-0000.h
+++ b/include/configs/p2771-0000.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (c) 2013-2016, NVIDIA CORPORATION.
- *
- * SPDX-License-Identifier: GPL-2.0
  */
 
 #ifndef _P2771_0000_H
@@ -14,20 +13,28 @@
 /* High-level configuration options */
 #define CONFIG_TEGRA_BOARD_STRING      "NVIDIA P2771-0000"
 
-/* I2C */
-#define CONFIG_SYS_I2C_TEGRA
-
 /* Environment in eMMC, at the end of 2nd "boot sector" */
-#define CONFIG_SYS_MMC_ENV_DEV         0
-#define CONFIG_SYS_MMC_ENV_PART                2
-#define CONFIG_ENV_OFFSET              (-CONFIG_ENV_SIZE)
 
-/* PCI host support */
-#define CONFIG_CMD_PCI
+#define BOARD_EXTRA_ENV_SETTINGS \
+       "calculated_vars=kernel_addr_r fdt_addr_r scriptaddr pxefile_addr_r " \
+               "ramdisk_addr_r\0" \
+       "kernel_addr_r_align=00200000\0" \
+       "kernel_addr_r_offset=00080000\0" \
+       "kernel_addr_r_size=02000000\0" \
+       "kernel_addr_r_aliases=loadaddr\0" \
+       "fdt_addr_r_align=00200000\0" \
+       "fdt_addr_r_offset=00000000\0" \
+       "fdt_addr_r_size=00200000\0" \
+       "scriptaddr_align=00200000\0" \
+       "scriptaddr_offset=00000000\0" \
+       "scriptaddr_size=00200000\0" \
+       "pxefile_addr_r_align=00200000\0" \
+       "pxefile_addr_r_offset=00000000\0" \
+       "pxefile_addr_r_size=00200000\0" \
+       "ramdisk_addr_r_align=00200000\0" \
+       "ramdisk_addr_r_offset=00000000\0" \
+       "ramdisk_addr_r_size=02000000\0"
 
 #include "tegra-common-post.h"
 
-/* Crystal is 38.4MHz. clk_m runs at half that rate */
-#define COUNTER_FREQUENCY      19200000
-
 #endif