Rename CONFIG_EHCI_IS_TDI to CONFIG_USB_EHCI_IS_TDI

[platform/kernel/u-boot.git] / include / configs / p1_p2_rdb_pc.h

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index ba5b649..d3ac057 100644 (file)
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -14,7 +14,6 @@
 
 #if defined(CONFIG_TARGET_P1020RDB_PC)
 #define CONFIG_BOARDNAME "P1020RDB-PC"
-#define CONFIG_NAND_FSL_ELBC
 #define CONFIG_VSC7385_ENET
 #define CONFIG_SLIC
 #define __SW_BOOT_MASK         0x03
@@ -41,7 +40,6 @@
  */
 #if defined(CONFIG_TARGET_P1020RDB_PD)
 #define CONFIG_BOARDNAME "P1020RDB-PD"
-#define CONFIG_NAND_FSL_ELBC
 #define CONFIG_VSC7385_ENET
 #define CONFIG_SLIC
 #define __SW_BOOT_MASK         0x03
@@ -58,7 +56,6 @@
 
 #if defined(CONFIG_TARGET_P2020RDB)
 #define CONFIG_BOARDNAME "P2020RDB-PC"
-#define CONFIG_NAND_FSL_ELBC
 #define CONFIG_VSC7385_ENET
 #define __SW_BOOT_MASK         0x03
 #define __SW_BOOT_NOR          0xc8
@@ -85,9 +82,7 @@
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SPL_COMMON_INIT_DDR
 #endif
-#endif
-
-#ifdef CONFIG_SPIFLASH
+#elif defined(CONFIG_SPIFLASH)
 #define CONFIG_SPL_SPI_FLASH_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
@@ -101,9 +96,7 @@
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SPL_COMMON_INIT_DDR
 #endif
-#endif
-
-#ifdef CONFIG_MTD_RAW_NAND
+#elif defined(CONFIG_MTD_RAW_NAND)
 #ifdef CONFIG_TPL_BUILD
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_NAND_INIT
@@ -157,7 +150,6 @@
 #else
 #define CONFIG_SYS_CLK_FREQ    66666666
 #endif
-#define CONFIG_DDR_CLK_FREQ    66666666
 
 #define CONFIG_HWCONFIG
 /*
@@ -179,7 +171,6 @@
 
 /* DDR Setup */
 #define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_DDR_SPD
 #define CONFIG_SYS_SPD_BUS_NUM 1
 #define SPD_EEPROM_ADDRESS 0x52
 
@@ -292,11 +283,6 @@
 
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
-#if defined(CONFIG_TARGET_P1020RDB_PD)
-#define CONFIG_SYS_NAND_BLOCK_SIZE     (128 * 1024)
-#else
-#define CONFIG_SYS_NAND_BLOCK_SIZE     (16 * 1024)
-#endif
 
 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
        | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
@@ -346,7 +332,6 @@
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN  (1024 * 1024)/* Reserved for malloc */
 
 #define CONFIG_SYS_CPLD_BASE   0xffa00000
 #ifdef CONFIG_PHYS_64BIT
@@ -464,36 +449,20 @@
 
 /* I2C */
 #if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_FSL_I2C_SPEED       400000
-#define CONFIG_SYS_FSL_I2C_SLAVE       0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET      0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED      400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE      0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET     0x3100
 #define CONFIG_SYS_I2C_NOPROBES                { {0, 0x29} }
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER  0
 #endif
 
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_I2C_EEPROM_ADDR     0x52
 #define CONFIG_SYS_SPD_BUS_NUM         1 /* For rom_loc and flash bank */
 
 /*
  * I2C2 EEPROM
  */
-#undef CONFIG_ID_EEPROM
 
 #define CONFIG_RTC_PT7C4338
 #define CONFIG_SYS_I2C_RTC_ADDR                0x68
 #define CONFIG_SYS_I2C_PCA9557_ADDR    0x18
 
 /* enable read and write access to EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 
 #if defined(CONFIG_PCI)
 /*
@@ -529,30 +498,6 @@
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xffc00000
 #endif
 
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_PCIE2_NAME          "PCIe SLOT"
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS       0xc0000000
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS       0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
-
-#define CONFIG_SYS_PCIE1_NAME          "mini PCIe SLOT"
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS       0x80000000
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS       0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
-#endif
-
 #define CONFIG_PCI_SCAN_SHOW   /* show pci devices on startup */
 #endif /* CONFIG_PCI */
 
@@ -631,7 +576,6 @@
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LOAD_ADDR   0x2000000       /* default load address */
 
 /*
  * For booting Linux, the board info and command line data
@@ -641,10 +585,6 @@
 #define CONFIG_SYS_BOOTMAPSZ   (64 << 20)      /* Initial Memory for Linux*/
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE   230400  /* speed to run kgdb serial port */
-#endif
-
 /*
  * Environment Configuration
  */
@@ -653,9 +593,6 @@
 #define CONFIG_BOOTFILE                "uImage"
 #define CONFIG_UBOOTPATH       u-boot.bin /* U-Boot image on TFTP server */
 
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR        1000000
-
 #ifdef __SW_BOOT_NOR
 #define __NOR_RST_CMD  \
 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
@@ -715,7 +652,7 @@ __stringify(__SD_RST_CMD)"\0" \
 __stringify(__NAND_RST_CMD)"\0" \
 __stringify(__PCIE_RST_CMD)"\0"
 
-#define CONFIG_NFSBOOTCOMMAND  \
+#define NFSBOOTCOMMAND \
 "setenv bootargs root=/dev/nfs rw "    \
 "nfsroot=$serverip:$rootpath " \
 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
@@ -724,7 +661,7 @@ __stringify(__PCIE_RST_CMD)"\0"
 "tftp $fdtaddr $fdtfile;"      \
 "bootm $loadaddr - $fdtaddr"
 
-#define CONFIG_HDBOOT  \
+#define HDBOOT \
 "setenv bootargs root=/dev/$bdev rw rootdelay=30 "     \
 "console=$consoledev,$baudrate $othbootargs;" \
 "usb start;"   \
@@ -757,7 +694,7 @@ __stringify(__PCIE_RST_CMD)"\0"
 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
 "bootm $norbootaddr - $norfdtaddr"
 
-#define CONFIG_RAMBOOTCOMMAND  \
+#define RAMBOOTCOMMAND \
 "setenv bootargs root=/dev/ram rw "    \
 "console=$consoledev,$baudrate $othbootargs " \
 "ramdisk_size=$ramdisk_size;"  \
@@ -766,6 +703,6 @@ __stringify(__PCIE_RST_CMD)"\0"
 "tftp $fdtaddr $fdtfile;"      \
 "bootm $loadaddr $ramdiskaddr $fdtaddr"
 
-#define CONFIG_BOOTCOMMAND     CONFIG_HDBOOT
+#define CONFIG_BOOTCOMMAND     HDBOOT
 
 #endif /* __CONFIG_H */