configs: Migrate CONFIG_SYS_MAX_FLASH_BANKS to Kconfig

[platform/kernel/u-boot.git] / include / configs / p1_p2_rdb_pc.h

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 6b4fc39..b993ec8 100644 (file)
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -102,12 +102,10 @@
 #define CONFIG_SPL_NAND_INIT
 #define CONFIG_SPL_COMMON_INIT_DDR
 #define CONFIG_SPL_MAX_SIZE            (128 << 10)
-#define CONFIG_TPL_TEXT_BASE           0xf8f81000
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    (832 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST     (0x11000000)
 #define CONFIG_SYS_NAND_U_BOOT_START   (0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS    ((128 + 128) << 10)
 #elif defined(CONFIG_SPL_BUILD)
 #define CONFIG_SPL_INIT_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
@@ -116,7 +114,6 @@
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    (128 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST     0xf8f80000
 #define CONFIG_SYS_NAND_U_BOOT_START   0xf8f80000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS    (128 << 10)
 #endif /* not CONFIG_TPL_BUILD */
 
 #define CONFIG_SPL_PAD_TO              0x20000
@@ -130,7 +127,7 @@
 
 #ifndef CONFIG_SYS_MONITOR_BASE
 #ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE        CONFIG_TPL_TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE        0xf8f81000
 #elif defined(CONFIG_SPL_BUILD)
 #define CONFIG_SYS_MONITOR_BASE        CONFIG_SPL_TEXT_BASE
 #else
@@ -140,17 +137,10 @@
 
 #define CONFIG_PCIE1   /* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2   /* PCIE controller 2 (slot 2) */
-#define CONFIG_SYS_PCI_64BIT   /* enable 64-bit PCI resources */
 
 #define CONFIG_SYS_SATA_MAX_DEVICE     2
 #define CONFIG_LBA48
 
-#if defined(CONFIG_TARGET_P2020RDB)
-#define CONFIG_SYS_CLK_FREQ    100000000
-#else
-#define CONFIG_SYS_CLK_FREQ    66666666
-#endif
-
 #define CONFIG_HWCONFIG
 /*
  * These can be toggled for performance analysis, otherwise use default.
@@ -264,8 +254,6 @@
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45      /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_MAX_FLASH_BANKS     1       /* number of banks */
-
 #undef CONFIG_SYS_FLASH_CHECKSUM
 #define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
@@ -352,22 +340,6 @@
                                 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
                                 OR_GPCM_EAD)
 
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
-#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR1_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
-#define CONFIG_SYS_OR1_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
-#else
-#define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
-#ifdef CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
-#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
-#endif
-#define CONFIG_SYS_BR3_PRELIM  CONFIG_CPLD_BR_PRELIM   /* CPLD Base Address */
-#define CONFIG_SYS_OR3_PRELIM  CONFIG_CPLD_OR_PRELIM   /* CPLD Options */
-
 /* Vsc7385 switch */
 #ifdef CONFIG_VSC7385_ENET
 #define __VSCFW_ADDR                   "vscfw_addr=ef000000"
@@ -385,9 +357,6 @@
                        OR_GPCM_XACS |  OR_GPCM_SCY_15 | OR_GPCM_SETA | \
                        OR_GPCM_TRLX |  OR_GPCM_EHTR | OR_GPCM_EAD)
 
-#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_VSC7385_BR_PRELIM
-#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_VSC7385_OR_PRELIM
-
 /* The size of the VSC7385 firmware image */
 #define CONFIG_VSC7385_IMAGE_SIZE      8192
 #endif
@@ -553,7 +522,6 @@
 #if defined(CONFIG_HAS_FSL_DR_USB)
 #ifdef CONFIG_USB_EHCI_HCD
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
 #endif
 #endif
 
@@ -565,8 +533,6 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR      CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #endif
 
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
 /*
  * Miscellaneous configurable options
  */
@@ -646,23 +612,6 @@ __stringify(__SD_RST_CMD)"\0" \
 __stringify(__NAND_RST_CMD)"\0" \
 __stringify(__PCIE_RST_CMD)"\0"
 
-#define NFSBOOTCOMMAND \
-"setenv bootargs root=/dev/nfs rw "    \
-"nfsroot=$serverip:$rootpath " \
-"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-"console=$consoledev,$baudrate $othbootargs;" \
-"tftp $loadaddr $bootfile;"    \
-"tftp $fdtaddr $fdtfile;"      \
-"bootm $loadaddr - $fdtaddr"
-
-#define HDBOOT \
-"setenv bootargs root=/dev/$bdev rw rootdelay=30 "     \
-"console=$consoledev,$baudrate $othbootargs;" \
-"usb start;"   \
-"ext2load usb 0:1 $loadaddr /boot/$bootfile;"  \
-"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"    \
-"bootm $loadaddr - $fdtaddr"
-
 #define CONFIG_USB_FAT_BOOT    \
 "setenv bootargs root=/dev/ram rw "    \
 "console=$consoledev,$baudrate $othbootargs " \
@@ -688,15 +637,4 @@ __stringify(__PCIE_RST_CMD)"\0"
 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
 "bootm $norbootaddr - $norfdtaddr"
 
-#define RAMBOOTCOMMAND \
-"setenv bootargs root=/dev/ram rw "    \
-"console=$consoledev,$baudrate $othbootargs " \
-"ramdisk_size=$ramdisk_size;"  \
-"tftp $ramdiskaddr $ramdiskfile;"      \
-"tftp $loadaddr $bootfile;"    \
-"tftp $fdtaddr $fdtfile;"      \
-"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND     HDBOOT
-
 #endif /* __CONFIG_H */